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Bump rocket-chip for L1-Fatbank integration

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L1System working with 4 dcache banks, 1 icache bank
This commit is contained in:
Vamber Yang
2023-11-06 22:08:14 -08:00
parent db4a2e50cd
commit 888ee57275
2 changed files with 16 additions and 1 deletions
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15
generators/chipyard/src/main/scala/config/RocketConfigs.scala
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@@ -48,6 +48,21 @@ class RadianceROMConfig extends Config(
new WithRadROMs(0x28000L, 0x8000, "sims/op_b.bin") ++
new AbstractConfig)
class RadianceFatBankROMConfig extends Config(
new freechips.rocketchip.subsystem.WithRadianceCores(1, useVxCache = false) ++
new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds = 16) ++
new freechips.rocketchip.subsystem.WithSimtLanes(nLanes = 4, nSrcIds = 16) ++
new freechips.rocketchip.subsystem.WithVortexFatBank(nBanks = 4)++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new chipyard.config.WithSystemBusWidth(bitWidth = 256) ++
new WithExtMemSize(BigInt("80000000", 16)) ++
new WithRadBootROM() ++
new WithRadROMs(0x7FFF0000L, 0x10000, "sims/args.bin") ++
new WithRadROMs(0x20000L, 0x8000, "sims/op_a.bin") ++
new WithRadROMs(0x28000L, 0x8000, "sims/op_b.bin") ++
new AbstractConfig)
class RadianceConfig extends Config(
new freechips.rocketchip.subsystem.WithRadianceCores(1, useVxCache = false) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++

2
generators/rocket-chip

Submodule generators/rocket-chip updated: 5bdc5819a2...5ca08fb816