diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
index 55bc3050..54e5b95a 100644
--- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
@@ -48,6 +48,21 @@ class RadianceROMConfig extends Config(
   new WithRadROMs(0x28000L, 0x8000, "sims/op_b.bin") ++
   new AbstractConfig)
 
+class RadianceFatBankROMConfig extends Config(
+  new freechips.rocketchip.subsystem.WithRadianceCores(1, useVxCache = false) ++
+  new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds = 16) ++
+  new freechips.rocketchip.subsystem.WithSimtLanes(nLanes = 4, nSrcIds = 16) ++
+  new freechips.rocketchip.subsystem.WithVortexFatBank(nBanks = 4)++
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.WithSystemBusWidth(bitWidth = 256) ++
+  new WithExtMemSize(BigInt("80000000", 16)) ++
+  new WithRadBootROM() ++
+  new WithRadROMs(0x7FFF0000L, 0x10000, "sims/args.bin") ++
+  new WithRadROMs(0x20000L, 0x8000, "sims/op_a.bin") ++
+  new WithRadROMs(0x28000L, 0x8000, "sims/op_b.bin") ++
+  new AbstractConfig)
+
+
 class RadianceConfig extends Config(
   new freechips.rocketchip.subsystem.WithRadianceCores(1, useVxCache = false) ++
   new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
diff --git a/generators/rocket-chip b/generators/rocket-chip
index 5bdc5819..5ca08fb8 160000
--- a/generators/rocket-chip
+++ b/generators/rocket-chip
@@ -1 +1 @@
-Subproject commit 5bdc5819a2c59aadd0eea838cc06cb6f98191fd1
+Subproject commit 5ca08fb8164f0e1a3f14285d601a44efc1214393