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syn and power yamls

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This commit is contained in:
Richard Yan
2024-07-20 23:57:49 -07:00
parent 8e5e717d76
commit 8518e33831
2 changed files with 5 additions and 5 deletions
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6
vlsi/example-asap7.yml
View File

@@ -2,12 +2,12 @@
# Technology used is ASAP7
vlsi.core.technology: "hammer.technology.asap7"
# Specify dir with ASAP7 Calibre deck tarball
technology.asap7.tarball_dir: "/path/to/asap7"
technology.asap7.tarball_dir: "/nscratch/hansung/asap7"
# Specify PDK and std cell install directories
# technology.asap7.pdk_install_dir: "/path/to/asap7/asap7PDK_r1p7"
# technology.asap7.stdcell_install_dir: "/path/to/asap7/asap7sc7p5t_27"
vlsi.core.max_threads: 12
vlsi.core.max_threads: 36
# General Hammer Inputs
@@ -17,7 +17,7 @@ vlsi.inputs.power_spec_type: "cpf"
# Specify clock signals
vlsi.inputs.clocks: [
{name: "clock_uncore_clock", period: "1ns", uncertainty: "0.1ns"}
{name: "clock_uncore", period: "2.5ns", uncertainty: "0.1ns"}
]
# Generate Make include to aid in flow

4
vlsi/example-design.yml
View File

@@ -2,7 +2,7 @@
# Generate Make include to aid in flow
vlsi.core.build_system: make
vlsi.core.max_threads: 12
vlsi.core.max_threads: 36
# Hammer will auto-generate a CPF for simple power designs; see hammer/src/hammer-vlsi/defaults.yml for more info
vlsi.inputs.power_spec_mode: "auto"
@@ -10,7 +10,7 @@ vlsi.inputs.power_spec_type: "cpf"
# Specify clock signals
vlsi.inputs.clocks: [
{name: "clock_uncore_clock", period: "2ns", uncertainty: "0.1ns"}
{name: "clock_uncore", period: "2.5ns", uncertainty: "0.1ns"}
]
# Specify pin properties