From 8518e338312df10d7d338b7529442bc956585835 Mon Sep 17 00:00:00 2001 From: Richard Yan Date: Sat, 20 Jul 2024 23:57:49 -0700 Subject: [PATCH] syn and power yamls --- vlsi/example-asap7.yml | 6 +++--- vlsi/example-design.yml | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/vlsi/example-asap7.yml b/vlsi/example-asap7.yml index 6fc819aa..56f381f9 100644 --- a/vlsi/example-asap7.yml +++ b/vlsi/example-asap7.yml @@ -2,12 +2,12 @@ # Technology used is ASAP7 vlsi.core.technology: "hammer.technology.asap7" # Specify dir with ASAP7 Calibre deck tarball -technology.asap7.tarball_dir: "/path/to/asap7" +technology.asap7.tarball_dir: "/nscratch/hansung/asap7" # Specify PDK and std cell install directories # technology.asap7.pdk_install_dir: "/path/to/asap7/asap7PDK_r1p7" # technology.asap7.stdcell_install_dir: "/path/to/asap7/asap7sc7p5t_27" -vlsi.core.max_threads: 12 +vlsi.core.max_threads: 36 # General Hammer Inputs @@ -17,7 +17,7 @@ vlsi.inputs.power_spec_type: "cpf" # Specify clock signals vlsi.inputs.clocks: [ - {name: "clock_uncore_clock", period: "1ns", uncertainty: "0.1ns"} + {name: "clock_uncore", period: "2.5ns", uncertainty: "0.1ns"} ] # Generate Make include to aid in flow diff --git a/vlsi/example-design.yml b/vlsi/example-design.yml index 3f46a443..773e1b3e 100644 --- a/vlsi/example-design.yml +++ b/vlsi/example-design.yml @@ -2,7 +2,7 @@ # Generate Make include to aid in flow vlsi.core.build_system: make -vlsi.core.max_threads: 12 +vlsi.core.max_threads: 36 # Hammer will auto-generate a CPF for simple power designs; see hammer/src/hammer-vlsi/defaults.yml for more info vlsi.inputs.power_spec_mode: "auto" @@ -10,7 +10,7 @@ vlsi.inputs.power_spec_type: "cpf" # Specify clock signals vlsi.inputs.clocks: [ - {name: "clock_uncore_clock", period: "2ns", uncertainty: "0.1ns"} + {name: "clock_uncore", period: "2.5ns", uncertainty: "0.1ns"} ] # Specify pin properties