wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Merge branch 'dev' of github.com:ucb-bar/chipyard into ariane-decouple

Browse Source
This commit is contained in:
Zitao Fang
2020-06-13 01:42:38 -07:00
parent 119a44b121 71f340a0af
commit 81724b3cc4
15 changed files with 37 additions and 56 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
.circleci/do-rtl-build.sh
View File

@@ -53,15 +53,20 @@ else
fi
# enter the verilator directory and build the specific config on remote server
run "make -C $REMOTE_SIM_DIR clean"
run "export RISCV=\"$TOOLS_DIR\"; \
export LD_LIBRARY_PATH=\"$LD_LIB_DIR\"; \
export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \
export VERILATOR_ROOT=\"$REMOTE_VERILATOR_DIR\"; \
export COURSIER_CACHE=\"$REMOTE_WORK_DIR/.coursier-cache\"; \
make -C $REMOTE_SIM_DIR clean; \
make -j$REMOTE_MAKE_NPROC -C $REMOTE_SIM_DIR JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" ${mapping[$1]}"
run "rm -rf $REMOTE_CHIPYARD_DIR/project"
# copy back the final build
run "rm -rf $REMOTE_CHIPYARD_DIR/project"
# copy back the final build
mkdir -p $LOCAL_CHIPYARD_DIR
copy $SERVER:$REMOTE_CHIPYARD_DIR/ $LOCAL_CHIPYARD_DIR

4
.circleci/run-tests.sh
View File

@@ -93,10 +93,10 @@ case $1 in
make -C $LOCAL_SIM_DIR ${mapping[$1]} BINARY=$LOCAL_CHIPYARD_DIR/tests/nvdla.riscv run-binary
;;
icenet)
make run-none-fast -C $LOCAL_SIM_DIR ${mapping[$1]}
make run-binary-fast BINARY=none -C $LOCAL_SIM_DIR ${mapping[$1]}
;;
testchipip)
make run-none-fast -C $LOCAL_SIM_DIR ${mapping[$1]}
make run-binary-fast BINARY=none -C $LOCAL_SIM_DIR ${mapping[$1]}
;;
*)
echo "No set of tests for $1. Did you spell it right?"

34
common.mk
View File

@@ -3,6 +3,14 @@
#########################################################################################
SHELL=/bin/bash
ifndef RISCV
$(error RISCV is unset. You must set RISCV yourself, or through the Chipyard auto-generated env file)
else
$(info Running with RISCV=$(RISCV))
endif
#########################################################################################
# extra make variables/rules from subprojects
#
@@ -129,34 +137,30 @@ verilog: $(sim_vsrcs)
# helper rules to run simulations
#########################################################################################
.PHONY: run-binary run-binary-fast run-binary-debug run-fast
run-binary: $(sim)
run-binary: $(output_dir) $(sim)
(set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $(BINARY) </dev/null 2> >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log)
#########################################################################################
# helper rules to run simulator as fast as possible
#########################################################################################
run-binary-fast: $(sim)
run-binary-fast: $(output_dir) $(sim)
(set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(PERMISSIVE_OFF) $(BINARY) </dev/null | tee $(sim_out_name).log)
#########################################################################################
# helper rules to run simulator with as much debug info as possible
#########################################################################################
run-binary-debug: $(sim_debug)
run-binary-debug: $(output_dir) $(sim_debug)
(set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) $(WAVEFORM_FLAG) $(PERMISSIVE_OFF) $(BINARY) </dev/null 2> >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log)
run-fast: run-asm-tests-fast run-bmark-tests-fast
run-none: $(output_dir)/none.out
run-none-fast: $(output_dir)/none.run
run-none-debug: $(output_dir)/none.vpd
#########################################################################################
# run assembly/benchmarks rules
#########################################################################################
$(output_dir)/%: $(RISCV)/riscv64-unknown-elf/share/riscv-tests/isa/%
mkdir -p $(output_dir)
$(output_dir):
mkdir -p $@
$(output_dir)/%: $(RISCV)/riscv64-unknown-elf/share/riscv-tests/isa/% $(output_dir)
ln -sf $< $@
$(output_dir)/%.run: $(output_dir)/% $(sim)
@@ -165,14 +169,6 @@ $(output_dir)/%.run: $(output_dir)/% $(sim)
$(output_dir)/%.out: $(output_dir)/% $(sim)
(set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $< </dev/null 2> >(spike-dasm > $@) | tee $<.log)
$(output_dir)/none.run: $(sim)
mkdir -p $(output_dir)
(set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(PERMISSIVE_OFF) $< </dev/null | tee $<.log) && touch $@
$(output_dir)/none.out: $(sim)
mkdir -p $(output_dir)
(set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) none </dev/null 2> >(spike-dasm > $@) | tee $(output_dir)/none.log)
#########################################################################################
# include build/project specific makefrags made from the generator
#########################################################################################

2
generators/sha3

Submodule generators/sha3 updated: a94dcf3ae0...762d9d08f8

2
generators/testchipip

Submodule generators/testchipip updated: 4b15061b6f...bb038feaa1

15
generators/utilities/src/main/resources/csrc/emulator.cc
View File

@@ -35,7 +35,6 @@
extern tsi_t* tsi;
extern dtm_t* dtm;
extern remote_bitbang_t * jtag;
extern int dramsim;
static uint64_t trace_count = 0;
bool verbose = false;
@@ -51,11 +50,6 @@ double sc_time_stamp()
return trace_count;
}
extern "C" int vpi_get_vlog_info(void* arg)
{
return 0;
}
static void usage(const char * program_name)
{
printf("Usage: %s [EMULATOR OPTION]... [VERILOG PLUSARG]... [HOST OPTION]... BINARY [TARGET OPTION]...\n",
@@ -125,7 +119,6 @@ int main(int argc, char** argv)
char ** htif_argv = NULL;
int verilog_plusargs_legal = 1;
dramsim = 0;
opterr = 1;
while (1) {
@@ -136,7 +129,6 @@ int main(int argc, char** argv)
{"seed", required_argument, 0, 's' },
{"rbb-port", required_argument, 0, 'r' },
{"verbose", no_argument, 0, 'V' },
{"dramsim", no_argument, 0, 'D' },
{"permissive", no_argument, 0, 'p' },
{"permissive-off", no_argument, 0, 'o' },
#if VM_TRACE
@@ -147,9 +139,9 @@ int main(int argc, char** argv)
};
int option_index = 0;
#if VM_TRACE
int c = getopt_long(argc, argv, "-chm:s:r:v:Vx:Dpo", long_options, &option_index);
int c = getopt_long(argc, argv, "-chm:s:r:v:Vx:po", long_options, &option_index);
#else
int c = getopt_long(argc, argv, "-chm:s:r:VDpo", long_options, &option_index);
int c = getopt_long(argc, argv, "-chm:s:r:Vpo", long_options, &option_index);
#endif
if (c == -1) break;
retry:
@@ -162,7 +154,6 @@ int main(int argc, char** argv)
case 's': random_seed = atoi(optarg); break;
case 'r': rbb_port = atoi(optarg); break;
case 'V': verbose = true; break;
case 'D': dramsim = 1; break;
case 'p': opterr = 0; break;
case 'o': opterr = 1; break;
#if VM_TRACE
@@ -198,8 +189,6 @@ int main(int argc, char** argv)
#endif
else if (arg.substr(0, 12) == "+cycle-count")
c = 'c';
else if (arg == "+dramsim")
c = 'D';
else if (arg == "+permissive")
c = 'p';
else if (arg == "+permissive-off")

4
sims/vcs/Makefile
View File

@@ -62,10 +62,6 @@ $(sim_debug): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS)
$(output_dir)/%.vpd: $(output_dir)/% $(sim_debug)
(set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) +vcdplusfile=$@ $(PERMISSIVE_OFF) $< </dev/null 2> >(spike-dasm > $<.out) | tee $<.log)
$(output_dir)/none.vpd: $(sim_debug)
mkdir -p $(output_dir)
(set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) +vcdplusfile=$@ $(PERMISSIVE_OFF) none </dev/null 2> >(spike-dasm > $(output_dir)/none.out) | tee $(output_dir)/none.log)
#########################################################################################
# general cleanup rule
#########################################################################################

1
sims/vcs/dramsim2_ini
View File

@@ -1 +0,0 @@
../../generators/testchipip/src/main/resources/dramsim2_ini

7
sims/verilator/Makefile
View File

@@ -87,6 +87,7 @@ TIMESCALE_OPTS := $(shell verilator --version | perl -lne 'if (/(\d.\d+)/ && $$1
VERILATOR_NONCC_OPTS = \
$(TIMESCALE_OPTS) \
--top-module $(VLOG_MODEL) \
--vpi \
-Wno-fatal \
$(shell if ! grep -iq "module.*ariane" $(build_dir)/*.*v; then echo "$(CHIPYARD_VERILATOR_FLAGS)"; else echo "$(ARIANE_VERILATOR_FLAGS)"; fi) \
--output-split 10000 \
@@ -146,12 +147,6 @@ $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug)
vcd2vpd $@.vcd $@ > /dev/null &
(set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) -v$@.vcd $(PERMISSIVE_OFF) $< </dev/null 2> >(spike-dasm > $<.out) | tee $<.log)
$(output_dir)/none.vpd: $(sim_debug)
mkdir -p $(output_dir)
rm -f $@.vcd && mkfifo $@.vcd
vcd2vpd $@.vcd $@ > /dev/null &
(set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) -v$@.vcd $(PERMISSIVE_OFF) none </dev/null 2> >(spike-dasm > $(output_dir)/none.out) | tee $(output_dir)/none.log)
#########################################################################################
# general cleanup rule
#########################################################################################

1
sims/verilator/dramsim2_ini
View File

@@ -1 +0,0 @@
../../generators/testchipip/src/main/resources/dramsim2_ini

4
variables.mk
View File

@@ -139,9 +139,9 @@ output_dir=$(sim_dir)/output/$(long_name)
PERMISSIVE_ON=+permissive
PERMISSIVE_OFF=+permissive-off
BINARY ?=
override SIM_FLAGS += +dramsim +max-cycles=$(timeout_cycles)
override SIM_FLAGS += +dramsim +dramsim_ini_dir=$(TESTCHIP_DIR)/src/main/resources/dramsim2_ini +max-cycles=$(timeout_cycles)
VERBOSE_FLAGS ?= +verbose
sim_out_name = $(subst $() $(),_,$(notdir $(basename $(BINARY))).$(long_name))
sim_out_name = $(output_dir)/$(subst $() $(),_,$(notdir $(basename $(BINARY))))
#########################################################################################
# build output directory for compilation

6
vlsi/Makefile
View File

@@ -99,8 +99,6 @@ SIM_TIMING_CONF = $(OBJ_DIR)/sim-timing-inputs.yml
include $(vlsi_dir)/sim.mk
$(SIM_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) $(dramsim_lib)
mkdir -p $(dir $@)
mkdir -p $(OBJ_DIR)/$(HAMMER_SIM_RUN_DIR)/$(notdir $(BINARY))
ln -sf $(base_dir)/generators/testchipip/src/main/resources/dramsim2_ini $(OBJ_DIR)/$(HAMMER_SIM_RUN_DIR)/$(notdir $(BINARY))/dramsim2_ini
echo "sim.inputs:" > $@
echo " top_module: $(VLSI_TOP)" >> $@
echo " input_files:" >> $@
@@ -131,7 +129,9 @@ $(SIM_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_file
echo ' - "'$$x'"' >> $@; \
done
echo " execution_flags_meta: 'append'" >> $@
ifneq ($(BINARY), )
echo " benchmarks: ['$(BINARY)']" >> $@
endif
echo " tb_dut: 'testHarness.$(VLSI_HARNESS_DUT_NAME)'" >> $@
$(SIM_DEBUG_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files)
@@ -160,12 +160,14 @@ $(POWER_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_fi
echo "power.inputs:" > $@
echo " tb_dut: 'testHarness/$(VLSI_HARNESS_DUT_NAME)'" >> $@
echo " database: '$(OBJ_DIR)/par-rundir/$(VLSI_TOP)_FINAL'" >> $@
ifneq ($(BINARY), )
echo " saifs: [" >> $@
echo " '$(OBJ_DIR)/sim-par-rundir/$(notdir $(BINARY))/ucli.saif'" >> $@
echo " ]" >> $@
echo " waveforms: [" >> $@
#echo " '$(OBJ_DIR)/sim-par-rundir/$(notdir $(BINARY))/$(sim_out_name).vcd'" >> $@
echo " ]" >> $@
endif
echo " start_times: ['0ns']" >> $@
echo " end_times: [" >> $@
echo " '`bc <<< $(timeout_cycles)*$(CLOCK_PERIOD)`ns'" >> $@

2
vlsi/hammer

Submodule vlsi/hammer updated: 9d83bbadc0...bd94e1ed7a

2
vlsi/hammer-cadence-plugins

Submodule vlsi/hammer-cadence-plugins updated: f644138bab...d905828d68

2
vlsi/hammer-synopsys-plugins

Submodule vlsi/hammer-synopsys-plugins updated: ef163445ee...e5ec0da8ad