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Add WithCoalescer to SoC config

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This commit is contained in:
Hansung Kim
2023-05-12 01:19:19 -07:00
parent dc4b8bd615
commit 7ed3d294c8
2 changed files with 5 additions and 2 deletions
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5
generators/chipyard/src/main/scala/config/GPUConfig.scala
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@@ -6,7 +6,10 @@ import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
class MemtraceCoreConfig extends Config( class MemtraceCoreConfig extends Config(
// Memtrace // Memtrace
new freechips.rocketchip.subsystem.WithMemtraceCore("vecadd.core1.thread4.trace", new freechips.rocketchip.subsystem.WithMemtraceCore("vecadd.core1.thread4.trace",
traceHasSource = true) ++ traceHasSource = false) ++
// new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.trace",
// traceHasSource = false) ++
new freechips.rocketchip.subsystem.WithCoalescer ++
new freechips.rocketchip.subsystem.WithNLanes(4) ++ new freechips.rocketchip.subsystem.WithNLanes(4) ++
// L2 // L2
new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++ new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++

2
generators/rocket-chip

Submodule generators/rocket-chip updated: 640a58b7a9...23b5ad37e4