From 7ed3d294c8961037762cef276b37ddc315164c7e Mon Sep 17 00:00:00 2001
From: Hansung Kim <hansung_kim@berkeley.edu>
Date: Fri, 12 May 2023 01:19:19 -0700
Subject: [PATCH] Add WithCoalescer to SoC config

---
 generators/chipyard/src/main/scala/config/GPUConfig.scala | 5 ++++-
 generators/rocket-chip                                    | 2 +-
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/generators/chipyard/src/main/scala/config/GPUConfig.scala b/generators/chipyard/src/main/scala/config/GPUConfig.scala
index a7ffd876..11ae3241 100644
--- a/generators/chipyard/src/main/scala/config/GPUConfig.scala
+++ b/generators/chipyard/src/main/scala/config/GPUConfig.scala
@@ -6,7 +6,10 @@ import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
 class MemtraceCoreConfig extends Config(
   // Memtrace
   new freechips.rocketchip.subsystem.WithMemtraceCore("vecadd.core1.thread4.trace",
-    traceHasSource = true) ++
+    traceHasSource = false) ++
+  // new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.trace",
+  //   traceHasSource = false) ++
+  new freechips.rocketchip.subsystem.WithCoalescer ++
   new freechips.rocketchip.subsystem.WithNLanes(4) ++
   // L2
   new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
diff --git a/generators/rocket-chip b/generators/rocket-chip
index 640a58b7..23b5ad37 160000
--- a/generators/rocket-chip
+++ b/generators/rocket-chip
@@ -1 +1 @@
-Subproject commit 640a58b7a96eaf7a0893f2c6870d9a6b2925c8aa
+Subproject commit 23b5ad37e4a17de0b575d20011a5a0dd18ed54a9