From 7e70e3525fe9ee54355997851ee044a97ed7ef79 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Tue, 17 Apr 2018 15:10:31 -0700 Subject: [PATCH] move bootrom to testchipip --- Makefrag | 3 +- bootrom/.gitignore | 2 -- bootrom/Makefile | 27 ---------------- bootrom/bootrom.S | 46 --------------------------- bootrom/bootrom.rv32.img | Bin 144 -> 0 bytes bootrom/bootrom.rv64.img | Bin 148 -> 0 bytes bootrom/linker.ld | 9 ------ src/main/scala/example/Configs.scala | 2 +- testchipip | 2 +- verisim/Makefile | 11 +++---- vsim/Makefile | 13 +++----- 11 files changed, 13 insertions(+), 102 deletions(-) delete mode 100644 bootrom/.gitignore delete mode 100644 bootrom/Makefile delete mode 100644 bootrom/bootrom.S delete mode 100755 bootrom/bootrom.rv32.img delete mode 100755 bootrom/bootrom.rv64.img delete mode 100644 bootrom/linker.ld diff --git a/Makefrag b/Makefrag index 494b2238..53ee2bd1 100644 --- a/Makefrag +++ b/Makefrag @@ -31,8 +31,9 @@ $(FIRRTL_JAR): $(call lookup_scala_srcs, $(ROCKETCHIP_DIR)/firrtl/src/main/scala cp -p $(FIRRTL_JAR) $(ROCKETCHIP_DIR)/lib build_dir=$(sim_dir)/generated-src +testchip_dir = $(base_dir)/testchipip -bootrom_img = $(base_dir)/bootrom/bootrom.rv64.img $(base_dir)/bootrom/bootrom.rv32.img +include $(testchip_dir)/Makefrag CHISEL_ARGS ?= diff --git a/bootrom/.gitignore b/bootrom/.gitignore deleted file mode 100644 index 3b54c5ff..00000000 --- a/bootrom/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -*.elf -*.dump diff --git a/bootrom/Makefile b/bootrom/Makefile deleted file mode 100644 index 02052992..00000000 --- a/bootrom/Makefile +++ /dev/null @@ -1,27 +0,0 @@ -bootrom_img = bootrom.rv64.img bootrom.rv32.img -bootrom_dump = bootrom.rv64.dump bootrom.rv32.dump - -GCC=riscv64-unknown-elf-gcc -CFLAGS_RV64=-mabi=lp64 -march=rv64ima -CFLAGS_RV32=-mabi=ilp32 -march=rv32ima -OBJCOPY=riscv64-unknown-elf-objcopy -OBJDUMP=riscv64-unknown-elf-objdump - -img: $(bootrom_img) - -dump: $(bootrom_dump) - -%.img: %.elf - $(OBJCOPY) -O binary --change-addresses=-0x10000 $< $@ - -%.rv32.elf: %.S linker.ld - $(GCC) $(CFLAGS_RV32) -Tlinker.ld $< -nostdlib -static -o $@ - -%.rv64.elf: %.S linker.ld - $(GCC) $(CFLAGS_RV64) -Tlinker.ld $< -nostdlib -static -o $@ - -%.dump: %.elf - $(OBJDUMP) -d $< > $@ - -clean: - rm -f *.elf *.dump *.img diff --git a/bootrom/bootrom.S b/bootrom/bootrom.S deleted file mode 100644 index d2c28fb3..00000000 --- a/bootrom/bootrom.S +++ /dev/null @@ -1,46 +0,0 @@ -#define DRAM_BASE 0x80000000 - -.section .text.start, "ax", @progbits -.globl _start -_start: - li a1, 0x2000000 // base address of clint - csrr a0, mhartid - bnez a0, boot_core - - addi a2, a1, 4 - li a3, 1 -interrupt_loop: - sw a3, 0(a2) - addi a2, a2, 4 - lw a3, -4(a2) - bnez a3, interrupt_loop - j boot_core - -.section .text.hang, "ax", @progbits -.globl _hang -_hang: - // This boot ROM doesn't know about any boot devices, so it just spins, - // waiting for the serial interface to load the program and interrupt it - la a0, _start - csrw mtvec, a0 - li a0, 8 // MIE or MSIP bit - csrw mie, a0 // set only MSIP in mie CSR - csrw mideleg, zero // no delegation - csrs mstatus, a0 // set MIE in mstatus CSR -wfi_loop: - wfi - j wfi_loop - -boot_core: - sll a0, a0, 2 // offset for hart msip - add a0, a0, a1 - sw zero, 0(a0) // clear the interrupt - li a0, DRAM_BASE // program reset vector - csrw mepc, a0 // return from interrupt to start of user program - csrr a0, mhartid // hartid for next level bootloader - la a1, _dtb // dtb address for next level bootloader - li a2, 0x80 // set mstatus MPIE to 0 - csrc mstatus, a2 - mret - -_dtb: diff --git a/bootrom/bootrom.rv32.img b/bootrom/bootrom.rv32.img deleted file mode 100755 index d0ca9641393167bcfdc69a5aa800a98e12627fd9..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 144 zcmdna%D_~t>hLj{g_R+np@CJn&6Qy?n*f8d!ZikAHaCW5wPXJu&tm(R&v1a50Sgdk zWnd6yW&Kku5NaUI+Q3jO;A&7TU|>+Jz-my;5Fn8M;r@SNQB?+G)~!G@SsBb(85)WO bL`^_;P6z6p-0I3G%*Mb`Y`_LouV4TG@~R&i diff --git a/bootrom/bootrom.rv64.img b/bootrom/bootrom.rv64.img deleted file mode 100755 index be6c55428d0c9357c3392767654345685d40c551..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 148 zcmdna%D_~t>hLj{g_R+np@CJn&6Qy?n*f8d!ZikAHaCW5wPXJu&tm(R&v1a50Sgdk zWnd6yW&Kku5NaUI+Q3jO;A&7TU|>+Jz-my;5Fn8M;r@SNQB?+G)~!G@SsA2R1sH@y fzcLmJh?;=xoetDLxz&|Xn2mv>*nkbFN5KF9WnUkx diff --git a/bootrom/linker.ld b/bootrom/linker.ld deleted file mode 100644 index 99566b73..00000000 --- a/bootrom/linker.ld +++ /dev/null @@ -1,9 +0,0 @@ -SECTIONS -{ - ROM_BASE = 0x10000; /* ... but actually position independent */ - - . = ROM_BASE; - .text.start : { *(.text.start) } - . = ROM_BASE + 0x40; - .text.hang : { *(.text.hang) } -} diff --git a/src/main/scala/example/Configs.scala b/src/main/scala/example/Configs.scala index ee733986..8465247c 100644 --- a/src/main/scala/example/Configs.scala +++ b/src/main/scala/example/Configs.scala @@ -10,7 +10,7 @@ import testchipip._ class WithBootROM extends Config((site, here, up) => { case BootROMParams => BootROMParams( - contentFileName = s"./bootrom/bootrom.rv${site(XLen)}.img") + contentFileName = s"./testchipip/bootrom/bootrom.rv${site(XLen)}.img") }) object ConfigValName { diff --git a/testchipip b/testchipip index 9850a5cc..72f71dee 160000 --- a/testchipip +++ b/testchipip @@ -1 +1 @@ -Subproject commit 9850a5cce55567f8d0d7d3671fe60833360815be +Subproject commit 72f71dee93dfaea3bf4d9290899dbd7cad68994f diff --git a/verisim/Makefile b/verisim/Makefile index 8ab1100f..1ccf58e1 100644 --- a/verisim/Makefile +++ b/verisim/Makefile @@ -24,15 +24,12 @@ long_name = $(PROJECT).$(MODEL).$(CONFIG) sim_vsrcs = \ $(build_dir)/$(long_name).v \ - $(base_dir)/rocket-chip/vsrc/AsyncResetReg.v \ - $(base_dir)/testchipip/vsrc/SimSerial.v \ - $(base_dir)/testchipip/vsrc/SimBlockDevice.v \ + $(ROCKETCHIP_DIR)/vsrc/AsyncResetReg.v \ + $(testchip_vsrcs) sim_csrcs = \ - $(base_dir)/testchipip/csrc/SimSerial.cc \ - $(base_dir)/testchipip/csrc/SimBlockDevice.cc \ - $(base_dir)/testchipip/csrc/blkdev.cc \ - $(base_dir)/testchipip/csrc/verilator-harness.cc + $(testchip_dir)/csrc/verilator-harness.cc \ + $(testchip_csrcs) model_dir = $(build_dir)/$(long_name) model_dir_debug = $(build_dir)/$(long_name).debug diff --git a/vsim/Makefile b/vsim/Makefile index e6b14bd2..e2dee841 100644 --- a/vsim/Makefile +++ b/vsim/Makefile @@ -18,16 +18,13 @@ include $(base_dir)/Makefrag sim_vsrcs = \ $(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).v \ - $(base_dir)/rocket-chip/vsrc/TestDriver.v \ - $(base_dir)/rocket-chip/vsrc/AsyncResetReg.v \ - $(base_dir)/rocket-chip/vsrc/plusarg_reader.v \ - $(base_dir)/testchipip/vsrc/SimSerial.v \ - $(base_dir)/testchipip/vsrc/SimBlockDevice.v \ + $(ROCKETCHIP_DIR)/vsrc/TestDriver.v \ + $(ROCKETCHIP_DIR)/vsrc/AsyncResetReg.v \ + $(ROCKETCHIP_DIR)/vsrc/plusarg_reader.v \ + $(testchip_vsrcs) sim_csrcs = \ - $(base_dir)/testchipip/csrc/SimSerial.cc \ - $(base_dir)/testchipip/csrc/SimBlockDevice.cc \ - $(base_dir)/testchipip/csrc/blkdev.cc \ + $(testchip_csrcs) VCS = vcs -full64