From 7074420abaf90fa7ca413a3870e606cc1b96869b Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Fri, 21 Oct 2016 16:03:26 -0700 Subject: [PATCH] initial commit --- .gitignore | 4 +++ .gitmodules | 6 ++++ Makefrag | 40 ++++++++++++++++++++++ bootrom/.gitignore | 2 ++ bootrom/Makefile | 16 +++++++++ bootrom/bootrom.S | 35 ++++++++++++++++++++ bootrom/bootrom.img | Bin 0 -> 104 bytes bootrom/linker.ld | 5 +++ build.sbt | 7 ++++ generate-pkg-mk.sh | 16 +++++++++ rocket-chip | 1 + src/main/scala/Configs.scala | 18 ++++++++++ src/main/scala/TestHarness.scala | 37 +++++++++++++++++++++ src/main/scala/Top.scala | 24 ++++++++++++++ testchipip | 1 + vsim/.gitignore | 7 ++++ vsim/Makefile | 55 +++++++++++++++++++++++++++++++ 17 files changed, 274 insertions(+) create mode 100644 .gitignore create mode 100644 .gitmodules create mode 100644 Makefrag create mode 100644 bootrom/.gitignore create mode 100644 bootrom/Makefile create mode 100644 bootrom/bootrom.S create mode 100755 bootrom/bootrom.img create mode 100644 bootrom/linker.ld create mode 100644 build.sbt create mode 100755 generate-pkg-mk.sh create mode 160000 rocket-chip create mode 100644 src/main/scala/Configs.scala create mode 100644 src/main/scala/TestHarness.scala create mode 100644 src/main/scala/Top.scala create mode 160000 testchipip create mode 100644 vsim/.gitignore create mode 100644 vsim/Makefile diff --git a/.gitignore b/.gitignore new file mode 100644 index 00000000..313467d8 --- /dev/null +++ b/.gitignore @@ -0,0 +1,4 @@ +/Makefrag.pkgs +target +*.jar +*.stamp diff --git a/.gitmodules b/.gitmodules new file mode 100644 index 00000000..6398e111 --- /dev/null +++ b/.gitmodules @@ -0,0 +1,6 @@ +[submodule "rocket-chip"] + path = rocket-chip + url = git@github.com:ucb-bar/rocket-chip.git +[submodule "testchipip"] + path = testchipip + url = git@github.com:ucb-bar/testchipip.git diff --git a/Makefrag b/Makefrag new file mode 100644 index 00000000..7d1867d0 --- /dev/null +++ b/Makefrag @@ -0,0 +1,40 @@ +lib_dir=$(base_dir)/lib + +ROCKETCHIP_DIR=$(base_dir)/rocket-chip +EXTRA_PACKAGES=testchipip + +rocketchip_stamp=$(base_dir)/lib/rocketchip.stamp +SBT ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -jar $(ROCKETCHIP_DIR)/sbt-launch.jar +extra_stamps = $(addprefix $(lib_dir)/,$(addsuffix .stamp,$(EXTRA_PACKAGES))) + +lookup_scala_srcs = $(shell find $(1)/ -iname "*.scala" 2> /dev/null) + +libs: $(rocketchip_stamp) $(extra_stamps) + +$(rocketchip_stamp): $(call lookup_scala_srcs, $(ROCKETCHIP_DIR)) + cd $(ROCKETCHIP_DIR) && $(SBT) pack + mkdir -p $(lib_dir) + cp $(ROCKETCHIP_DIR)/target/pack/lib/*.jar $(lib_dir) + touch $(rocketchip_stamp) + +-include $(base_dir)/Makefrag.pkgs + +$(base_dir)/Makefrag.pkgs: $(base_dir)/generate-pkg-mk.sh + bash $(base_dir)/generate-pkg-mk.sh $(EXTRA_PACKAGES) > $@ + +FIRRTL_JAR ?= $(ROCKETCHIP_DIR)/firrtl/utils/bin/firrtl.jar +FIRRTL ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -cp $(FIRRTL_JAR) firrtl.Driver + +$(FIRRTL_JAR): $(call lookup_scala_srcs, $(ROCKETCHIP_DIR)/firrtl/src/main/scala) + $(MAKE) -C $(ROCKETCHIP_DIR)/firrtl SBT="$(SBT)" root_dir=$(ROCKETCHIP_DIR)/firrtl build-scala + +build_dir=$(sim_dir)/generated-src + +CHISEL_ARGS ?= + +$(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).fir: $(rocketchip_stamp) $(extra_stamps) $(call lookup_scala_srcs,$(base_dir)/src/main/scala) + mkdir -p $(build_dir) + cd $(base_dir) && $(SBT) "run-main $(PROJECT).Generator $(CHISEL_ARGS) $(build_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)" + +$(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).v: $(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).fir $(FIRRTL_JAR) + $(FIRRTL) -i $< -o $@ -X verilog diff --git a/bootrom/.gitignore b/bootrom/.gitignore new file mode 100644 index 00000000..3b54c5ff --- /dev/null +++ b/bootrom/.gitignore @@ -0,0 +1,2 @@ +*.elf +*.dump diff --git a/bootrom/Makefile b/bootrom/Makefile new file mode 100644 index 00000000..19c1a404 --- /dev/null +++ b/bootrom/Makefile @@ -0,0 +1,16 @@ +bootrom_img = bootrom.img + +GCC=riscv64-unknown-elf-gcc +OBJCOPY=riscv64-unknown-elf-objcopy +OBJDUMP=riscv64-unknown-elf-objdump + +all: $(bootrom_img) + +%.img: %.elf + $(OBJCOPY) -O binary --change-addresses=-0x1000 --only-section .text $< $@ + +%.elf: %.S linker.ld + $(GCC) -Tlinker.ld $< -nostdlib -static -o $@ + +%.dump: %.elf + $(OBJDUMP) -d $< > $@ diff --git a/bootrom/bootrom.S b/bootrom/bootrom.S new file mode 100644 index 00000000..86aece92 --- /dev/null +++ b/bootrom/bootrom.S @@ -0,0 +1,35 @@ +.text +.global _start +_start: + // This boot ROM doesn't know about any boot devices, so it just spins, + // waiting for the serial interface to load the program and interrupt it + j setup_wfi_loop // reset vector + .word 0 // reserved + .word 0 // reserved + .word 0 // pointer to config string +default_trap_vec: + j boot_trap // default trap vector + .word 0 + .word 0 + .word 0 + +setup_wfi_loop: + la a0, default_trap_vec + csrw mtvec, a0 + li a0, 8 // MIE or MSIP bit + csrw mie, a0 // set only MSIP in mie CSR + csrw mideleg, zero // no delegation + csrs mstatus, a0 // set MIE in mstatus CSR +wfi_loop: + wfi + j wfi_loop + +boot_trap: + csrr a0, mhartid + sll a0, a0, 2 // offset for hart msip + li a1, 0x2000000 // base address of clint + add a0, a0, a1 + sw zero, 0(a0) // clear the interrupt + li a0, 0x80000000 // program reset vector + csrw mepc, a0 // return from interrupt to start of user program + mret diff --git a/bootrom/bootrom.img b/bootrom/bootrom.img new file mode 100755 index 0000000000000000000000000000000000000000..a258726f661ada3b034f2182ef8b5eceff5a19b3 GIT binary patch literal 104 zcmd02U|?cE0{ILM%t%}YaaINfVOG}v#R8!Q!mJGp#R9Gd#R3Kf#R{wj#S8%g`5*58 pFIIK pname match { + case BuildExampleTop => (p: Parameters) => LazyModule(new ExampleTop(p)) + case _ => throw new CDEMatchError + }) + +class SerialAdapterConfig extends Config( + new WithSerialAdapter ++ new rocketchip.BaseConfig) + +class DefaultExampleConfig extends Config( + new WithExampleTop ++ new SerialAdapterConfig) diff --git a/src/main/scala/TestHarness.scala b/src/main/scala/TestHarness.scala new file mode 100644 index 00000000..afbae389 --- /dev/null +++ b/src/main/scala/TestHarness.scala @@ -0,0 +1,37 @@ +package example + +import util.GeneratorApp +import diplomacy.LazyModule +import rocketchip._ +import testchipip._ +import chisel3._ +import cde.{Parameters, Field} + +case object BuildExampleTop extends Field[Parameters => ExampleTop] + +class TestHarness(implicit val p: Parameters) extends Module { + val io = new Bundle { + val success = Bool(OUTPUT) + } + + def buildTop(p: Parameters): ExampleTop = LazyModule(new ExampleTop(p)) + + val dut = p(BuildExampleTop)(p).module + val ser = Module(new SimSerialWrapper(p(SerialInterfaceWidth))) + + val nMemChannels = dut.io.mem_axi.size + for (axi <- dut.io.mem_axi) { + val mem = Module(new SimAXIMem(BigInt(p(ExtMemSize) / nMemChannels))) + mem.io.axi <> axi + } + + ser.io.serial <> dut.io.serial + io.success := ser.io.exit +} + +object Generator extends GeneratorApp { + val longName = names.topModuleProject + "." + + names.topModuleClass + "." + + names.configs + generateFirrtl +} diff --git a/src/main/scala/Top.scala b/src/main/scala/Top.scala new file mode 100644 index 00000000..1c82269e --- /dev/null +++ b/src/main/scala/Top.scala @@ -0,0 +1,24 @@ +package example + +import chisel3._ +import cde.Parameters +import diplomacy.LazyModule +import testchipip._ +import rocketchip._ + +class ExampleTop(q: Parameters) extends BaseTop(q) + with PeripheryBootROM with PeripheryCoreplexLocalInterrupter + with PeripherySerial with PeripheryMasterMem { + override lazy val module = Module( + new ExampleTopModule(p, this, new ExampleTopBundle(p))) +} + +class ExampleTopBundle(p: Parameters) extends BaseTopBundle(p) + with PeripheryBootROMBundle with PeripheryCoreplexLocalInterrupterBundle + with PeripheryMasterMemBundle with PeripherySerialBundle + +class ExampleTopModule(p: Parameters, l: ExampleTop, b: => ExampleTopBundle) + extends BaseTopModule(p, l, b) + with PeripheryBootROMModule with PeripheryCoreplexLocalInterrupterModule + with PeripheryMasterMemModule with PeripherySerialModule + with HardwiredResetVector with DirectConnection with NoDebug diff --git a/testchipip b/testchipip new file mode 160000 index 00000000..a3261102 --- /dev/null +++ b/testchipip @@ -0,0 +1 @@ +Subproject commit a326110250a3256c3ffd0ce9b39ae2c94cbf944c diff --git a/vsim/.gitignore b/vsim/.gitignore new file mode 100644 index 00000000..0037cb6b --- /dev/null +++ b/vsim/.gitignore @@ -0,0 +1,7 @@ +/DVEfiles +/csrc +/simv-* +/output +/generated-src +/ucli.key +/vc_hdrs.h diff --git a/vsim/Makefile b/vsim/Makefile new file mode 100644 index 00000000..4669465d --- /dev/null +++ b/vsim/Makefile @@ -0,0 +1,55 @@ +base_dir=$(abspath ..) +sim_dir=$(abspath .) + +PROJECT ?= example +MODEL ?= TestHarness +CONFIG ?= DefaultExampleConfig +CFG_PROJECT ?= $(PROJECT) +TB ?= TestDriver + +simv = simv-$(PROJECT)-$(CONFIG) +simv_debug = simv-$(PROJECT)-$(CONFIG)-debug + +default: $(simv) + +debug: $(simv_debug) + +include $(base_dir)/Makefrag + +sim_vsrcs = \ + $(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).v \ + $(base_dir)/testchipip/vsrc/TestDriver.v \ + $(base_dir)/testchipip/vsrc/SimSerial.v + +sim_csrcs = \ + $(base_dir)/testchipip/csrc/SimSerial.cc + +VCS = vcs -full64 + +VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1ns/10ps -quiet \ + +rad +v2k +vcs+lic+wait \ + +vc+list -CC "-I$(VCS_HOME)/include" \ + -CC "-I$(RISCV)/include" \ + -CC "-std=c++11" \ + -CC "-Wl,-rpath,$(RISCV)/lib" \ + $(RISCV)/lib/libfesvr.so \ + -sverilog \ + +incdir+$(generated_dir) \ + +define+CLOCK_PERIOD=1.0 $(sim_vsrcs) $(sim_csrcs) \ + +define+PRINTF_COND=$(TB).printf_cond \ + +define+STOP_COND=!$(TB).reset \ + +define+RANDOMIZE_MEM_INIT \ + +define+RANDOMIZE_REG_INIT \ + +define+RANDOMIZE_GARBAGE_ASSIGN \ + +define+RANDOMIZE_INVALID_ASSIGN \ + +libext+.v \ + +verilog: $(sim_vsrcs) + +$(simv): $(sim_vsrcs) $(sim_csrcs) + rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \ + -debug_pp + +$(simv_debug) : $(sim_vsrcs) $(sim_csrcs) + rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \ + +define+DEBUG -debug_pp