diff --git a/tapeout/src/test/scala/transforms/ResetInverterSpec.scala b/tapeout/src/test/scala/transforms/ResetInverterSpec.scala
index fe204288..9f23c3a8 100644
--- a/tapeout/src/test/scala/transforms/ResetInverterSpec.scala
+++ b/tapeout/src/test/scala/transforms/ResetInverterSpec.scala
@@ -3,7 +3,8 @@
 package barstools.tapeout.transforms
 
 import chisel3._
-import chisel3.stage.ChiselStage
+import chisel3.stage.{ChiselStage, ChiselGeneratorAnnotation}
+import firrtl.{EmittedFirrtlCircuitAnnotation, EmittedFirrtlModuleAnnotation}
 import org.scalatest.{FreeSpec, Matchers}
 
 class ExampleModuleNeedsResetInverted extends Module with ResetInverter {
@@ -20,14 +21,23 @@ class ExampleModuleNeedsResetInverted extends Module with ResetInverter {
 
 class ResetNSpec extends FreeSpec with Matchers {
   "Inverting reset needs to be done throughout module in Chirrtl" in {
-    val chirrtl = (new ChiselStage).emitChirrtl(new ExampleModuleNeedsResetInverted, Array("--no-run-firrtl"))
+    val chirrtl = (new ChiselStage).emitChirrtl(new ExampleModuleNeedsResetInverted)
     chirrtl should include("input reset :")
     (chirrtl should not).include("input reset_n :")
     (chirrtl should not).include("node reset = not(reset_n)")
   }
 
   "Inverting reset needs to be done throughout module when generating firrtl" in {
-    val firrtl = (new ChiselStage).emitFirrtl(new ExampleModuleNeedsResetInverted)
+    // generate low-firrtl
+    val firrtl = (new ChiselStage).execute(
+      Array("-X", "low"),
+      Seq(ChiselGeneratorAnnotation(() => new ExampleModuleNeedsResetInverted))
+    ).collect {
+      case EmittedFirrtlCircuitAnnotation(a) => a
+      case EmittedFirrtlModuleAnnotation(a)  => a
+    }.map(_.value)
+    .mkString("")
+
     firrtl should include("input reset_n :")
     firrtl should include("node reset = not(reset_n)")
     (firrtl should not).include("input reset :")