From 5c200ddb6efb4d9af1ed7cfa5c45f22a297adbb6 Mon Sep 17 00:00:00 2001
From: Howard Mao <zhehao.mao@gmail.com>
Date: Sun, 1 Oct 2017 22:20:20 +0000
Subject: [PATCH] bump rocket-chip and testchipip

---
 rocket-chip                              |  2 +-
 src/main/scala/example/Configs.scala     | 10 +++++-----
 src/main/scala/example/PWM.scala         |  4 ++--
 src/main/scala/example/TestHarness.scala |  4 ++--
 src/main/scala/example/Top.scala         |  2 +-
 testchipip                               |  2 +-
 6 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/rocket-chip b/rocket-chip
index 0ab5cb67..86a19532 160000
--- a/rocket-chip
+++ b/rocket-chip
@@ -1 +1 @@
-Subproject commit 0ab5cb67b3e80700f06a823225fccdadcf62be23
+Subproject commit 86a19532871b118ff2de9dcabb0938158cd0e48b
diff --git a/src/main/scala/example/Configs.scala b/src/main/scala/example/Configs.scala
index f02dc6e9..1dd00e52 100644
--- a/src/main/scala/example/Configs.scala
+++ b/src/main/scala/example/Configs.scala
@@ -7,17 +7,17 @@ import freechips.rocketchip.diplomacy.LazyModule
 import testchipip._
 
 class WithExampleTop extends Config((site, here, up) => {
-  case BuildTop => (p: Parameters) =>
+  case BuildTop => (clock: Clock, reset: Bool, p: Parameters) =>
     Module(LazyModule(new ExampleTop()(p)).module)
 })
 
 class WithPWM extends Config((site, here, up) => {
-  case BuildTop => (p: Parameters) =>
+  case BuildTop => (clock: Clock, reset: Bool, p: Parameters) =>
     Module(LazyModule(new ExampleTopWithPWM()(p)).module)
 })
 
 class WithBlockDeviceModel extends Config((site, here, up) => {
-  case BuildTop => (p: Parameters) => {
+  case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => {
     val top = Module(LazyModule(new ExampleTopWithBlockDevice()(p)).module)
     top.connectBlockDeviceModel()
     top
@@ -25,9 +25,9 @@ class WithBlockDeviceModel extends Config((site, here, up) => {
 })
 
 class WithSimBlockDevice extends Config((site, here, up) => {
-  case BuildTop => (p: Parameters) => {
+  case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => {
     val top = Module(LazyModule(new ExampleTopWithBlockDevice()(p)).module)
-    top.connectSimBlockDevice()
+    top.connectSimBlockDevice(clock, reset)
     top
   }
 })
diff --git a/src/main/scala/example/PWM.scala b/src/main/scala/example/PWM.scala
index 1e501d2e..3a8ebf72 100644
--- a/src/main/scala/example/PWM.scala
+++ b/src/main/scala/example/PWM.scala
@@ -37,7 +37,7 @@ trait PWMTLBundle extends Bundle {
   val pwmout = Output(Bool())
 }
 
-trait PWMTLModule extends Module with HasRegMap {
+trait PWMTLModule extends HasRegMap {
   val io: PWMTLBundle
   implicit val p: Parameters
   def params: PWMParams
@@ -85,7 +85,7 @@ trait HasPeripheryPWM extends HasPeripheryBus {
   pwm.node := pbus.toVariableWidthSlaves
 }
 
-trait HasPeripheryPWMModuleImp extends LazyMultiIOModuleImp {
+trait HasPeripheryPWMModuleImp extends LazyModuleImp {
   implicit val p: Parameters
   val outer: HasPeripheryPWM
 
diff --git a/src/main/scala/example/TestHarness.scala b/src/main/scala/example/TestHarness.scala
index c0c0e67e..522f4993 100644
--- a/src/main/scala/example/TestHarness.scala
+++ b/src/main/scala/example/TestHarness.scala
@@ -5,14 +5,14 @@ import freechips.rocketchip.diplomacy.LazyModule
 import freechips.rocketchip.config.{Field, Parameters}
 import testchipip.GeneratorApp
 
-case object BuildTop extends Field[Parameters => ExampleTopModule[ExampleTop]]
+case object BuildTop extends Field[(Clock, Bool, Parameters) => ExampleTopModule[ExampleTop]]
 
 class TestHarness(implicit val p: Parameters) extends Module {
   val io = IO(new Bundle {
     val success = Output(Bool())
   })
 
-  val dut = p(BuildTop)(p)
+  val dut = p(BuildTop)(clock, reset.toBool, p)
   dut.connectSimAXIMem()
   io.success := dut.connectSimSerial()
 }
diff --git a/src/main/scala/example/Top.scala b/src/main/scala/example/Top.scala
index 5aa0a128..bacc5a02 100644
--- a/src/main/scala/example/Top.scala
+++ b/src/main/scala/example/Top.scala
@@ -9,7 +9,7 @@ import testchipip._
 class ExampleTop(implicit p: Parameters) extends RocketCoreplex
     with HasMasterAXI4MemPort
     with HasPeripheryBootROM
-    with HasPeripheryErrorSlave
+    with HasSystemErrorSlave
     with HasNoDebug
     with HasPeripherySerial {
   override lazy val module = new ExampleTopModule(this)
diff --git a/testchipip b/testchipip
index 1cb8dec5..9dd1e3a5 160000
--- a/testchipip
+++ b/testchipip
@@ -1 +1 @@
-Subproject commit 1cb8dec51df7ca83e9df7b4820499c1b7a459181
+Subproject commit 9dd1e3a5161fb59763968f8bbc99798a2da23f71