diff --git a/generators/boom b/generators/boom
index a88fe70c..1d4d0cda 160000
--- a/generators/boom
+++ b/generators/boom
@@ -1 +1 @@
-Subproject commit a88fe70c81c33fb4773d52a529633029fa6eb9af
+Subproject commit 1d4d0cda50969a0c46f1807cc7b2201bbf42a6f3
diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala
index 17ac06e6..ed2a86c5 100644
--- a/generators/firechip/src/main/scala/TargetConfigs.scala
+++ b/generators/firechip/src/main/scala/TargetConfigs.scala
@@ -80,6 +80,10 @@ class WithBoomL2TLBs(entries: Int) extends Config((site, here, up) => {
   ))
 })
 
+class WithBoomEnableTrace extends Config((site, here, up) => {
+  case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true))
+})
+
 // Disables clock-gating; doesn't play nice with our FAME-1 pass
 class WithoutClockGating extends Config((site, here, up) => {
   case DebugModuleKey => up(DebugModuleKey, site).map(_.copy(clockGate = false))
@@ -176,6 +180,7 @@ class FireSimBoomConfig extends Config(
   new WithNICKey ++
   new WithSerial ++
   new WithBlockDevice ++
+  new WithBoomEnableTrace ++
   new WithBoomL2TLBs(1024) ++
   new WithoutClockGating ++
   new WithDefaultMemModel ++
diff --git a/generators/firechip/src/main/scala/TargetMixins.scala b/generators/firechip/src/main/scala/TargetMixins.scala
index c3982d95..be93bb7a 100644
--- a/generators/firechip/src/main/scala/TargetMixins.scala
+++ b/generators/firechip/src/main/scala/TargetMixins.scala
@@ -45,7 +45,7 @@ trait HasTraceIOImp extends LazyModuleImp {
   // Enabled to test TracerV trace capture
   if (p(PrintTracePort)) {
     val traceprint = Wire(UInt(512.W))
-    traceprint := Cat(traceIO.traces.map(_.asUInt))
+    traceprint := Cat(traceIO.traces.map(_.reverse.asUInt))
     printf("TRACEPORT: %x\n", traceprint)
   }
 }