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simple bug fix

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This commit is contained in:
Donggyu Kim
2017-07-27 14:34:57 -07:00
committed by edwardcwang
parent 484906b85c
commit 4fc829a570
1 changed files with 2 additions and 2 deletions
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4
macros/src/main/scala/Utils.scala
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@@ -43,8 +43,8 @@ class Macro(srcMacro: SRAMMacro) {
val firrtlPorts = srcMacro.ports map { new FirrtlMacroPort(_) }
val writers = firrtlPorts filter (p => p.isReader)
val readers = firrtlPorts filter (p => p.isWriter)
val writers = firrtlPorts filter (p => p.isWriter)
val readers = firrtlPorts filter (p => p.isReader)
val readwriters = firrtlPorts filter (p => p.isReadWriter)
val sortedPorts = writers ++ readers ++ readwriters