diff --git a/macros/src/main/scala/Utils.scala b/macros/src/main/scala/Utils.scala
index 450a33a4..36a8ce7c 100644
--- a/macros/src/main/scala/Utils.scala
+++ b/macros/src/main/scala/Utils.scala
@@ -43,8 +43,8 @@ class Macro(srcMacro: SRAMMacro) {
 
   val firrtlPorts = srcMacro.ports map { new FirrtlMacroPort(_) }
 
-  val writers = firrtlPorts filter (p => p.isReader)
-  val readers = firrtlPorts filter (p => p.isWriter)
+  val writers = firrtlPorts filter (p => p.isWriter)
+  val readers = firrtlPorts filter (p => p.isReader)
   val readwriters = firrtlPorts filter (p => p.isReadWriter)
 
   val sortedPorts = writers ++ readers ++ readwriters