connect extra ports

This commit is contained in:
Donggyu Kim
2017-07-04 17:15:38 -07:00
committed by edwardcwang
parent 98155dd831
commit 4f5a9ae02e
4 changed files with 113 additions and 6 deletions

View File

@@ -0,0 +1,35 @@
[
{
"type": "sram",
"name": "vendor_sram",
"depth": 1024,
"width": 8,
"ports": [
{
"clock port name": "clock",
"mask granularity": 8,
"output port name": "RW0O",
"input port name": "RW0I",
"address port name": "RW0A",
"mask port name": "RW0M",
"chip enable port name": "RW0E",
"write enable port name": "RW0W",
"clock port polarity": "positive edge",
"output port polarity": "active high",
"input port polarity": "active high",
"address port polarity": "active high",
"mask port polarity": "active high",
"chip enable port polarity": "active high",
"write enable port polarity": "active high"
}
],
"extra ports": [
{
"name": "sleep",
"type": "constant",
"width": 1,
"value": 0
}
]
}
]