From 4f5a9ae02e98c6fb9d59cc956b958a8c06cccfe0 Mon Sep 17 00:00:00 2001 From: Donggyu Kim Date: Tue, 4 Jul 2017 17:15:38 -0700 Subject: [PATCH] connect extra ports --- .../transforms/macros/MacroCompiler.scala | 7 ++- .../main/scala/transforms/macros/Utils.scala | 21 +++++-- .../resources/macros/lib-1024x8-sleep.json | 35 ++++++++++++ .../scala/transforms/macros/SplitDepth.scala | 56 +++++++++++++++++++ 4 files changed, 113 insertions(+), 6 deletions(-) create mode 100644 tapeout/src/test/resources/macros/lib-1024x8-sleep.json diff --git a/tapeout/src/main/scala/transforms/macros/MacroCompiler.scala b/tapeout/src/main/scala/transforms/macros/MacroCompiler.scala index b8b821c7..0330ab13 100644 --- a/tapeout/src/main/scala/transforms/macros/MacroCompiler.scala +++ b/tapeout/src/main/scala/transforms/macros/MacroCompiler.scala @@ -92,7 +92,12 @@ class MacroCompilerPass(memFile: Option[File], } for ((off, i) <- (0 until mem.depth.toInt by lib.depth.toInt).zipWithIndex) { for (j <- pairs.indices) { - stmts += WDefInstance(NoInfo, s"mem_${i}_${j}", lib.name, instType) + val name = s"mem_${i}_${j}" + stmts += WDefInstance(NoInfo, name, lib.name, instType) + // connect extra ports + stmts ++= lib.extraPorts map { case (portName, portValue) => + Connect(NoInfo, WSubField(WRef(name), portName), portValue) + } } for ((memPort, libPort) <- pairedPorts) { val addrMatch = selects get memPort.addressName match { diff --git a/tapeout/src/main/scala/transforms/macros/Utils.scala b/tapeout/src/main/scala/transforms/macros/Utils.scala index 7c3977c6..5a2e34e6 100644 --- a/tapeout/src/main/scala/transforms/macros/Utils.scala +++ b/tapeout/src/main/scala/transforms/macros/Utils.scala @@ -67,8 +67,8 @@ case class MacroPort( class Macro(lib: Map[String, Any]) { val name = lib("name").asInstanceOf[String] - val width = BigInt(lib("width").asInstanceOf[Double].toInt) - val depth = BigInt(lib("depth").asInstanceOf[Double].toInt) + val width = BigInt(lib("width").asInstanceOf[Double].toLong) + val depth = BigInt(lib("depth").asInstanceOf[Double].toLong) val ports = lib("ports").asInstanceOf[List[_]] map { x => val map = x.asInstanceOf[Map[String, Any]] MacroPort( @@ -88,15 +88,26 @@ class Macro(lib: Map[String, Any]) { map get "write enable port polarity", map get "mask port name" map (_.asInstanceOf[String]), map get "mask port polarity", - map get "mask granularity" map (x => BigInt(x.asInstanceOf[Double].toInt)), + map get "mask granularity" map (x => BigInt(x.asInstanceOf[Double].toLong)), width, depth ) } - private val modPorts = ports flatMap (_.ports) + val extraPorts = lib get "extra ports" match { + case None => Nil + case Some(p) => p.asInstanceOf[List[_]] map { x => + val map = x.asInstanceOf[Map[String, Any]] + assert(map("type").asInstanceOf[String] == "constant") // TODO: release it? + val name = map("name").asInstanceOf[String] + val width = BigInt(map("width").asInstanceOf[Double].toLong) + val value = BigInt(map("value").asInstanceOf[Double].toLong) + (name -> UIntLiteral(value, IntWidth(width))) + } + } + private val modPorts = (ports flatMap (_.ports)) ++ + (extraPorts map { case (name, value) => Port(NoInfo, name, Input, value.tpe) }) val blackbox = ExtModule(NoInfo, name, modPorts, name, Nil) def module(body: Statement) = Module(NoInfo, name, modPorts, body) - } object Utils { diff --git a/tapeout/src/test/resources/macros/lib-1024x8-sleep.json b/tapeout/src/test/resources/macros/lib-1024x8-sleep.json new file mode 100644 index 00000000..7736590d --- /dev/null +++ b/tapeout/src/test/resources/macros/lib-1024x8-sleep.json @@ -0,0 +1,35 @@ +[ + { + "type": "sram", + "name": "vendor_sram", + "depth": 1024, + "width": 8, + "ports": [ + { + "clock port name": "clock", + "mask granularity": 8, + "output port name": "RW0O", + "input port name": "RW0I", + "address port name": "RW0A", + "mask port name": "RW0M", + "chip enable port name": "RW0E", + "write enable port name": "RW0W", + "clock port polarity": "positive edge", + "output port polarity": "active high", + "input port polarity": "active high", + "address port polarity": "active high", + "mask port polarity": "active high", + "chip enable port polarity": "active high", + "write enable port polarity": "active high" + } + ], + "extra ports": [ + { + "name": "sleep", + "type": "constant", + "width": 1, + "value": 0 + } + ] + } +] diff --git a/tapeout/src/test/scala/transforms/macros/SplitDepth.scala b/tapeout/src/test/scala/transforms/macros/SplitDepth.scala index c5ef8e19..7a9f5b9d 100644 --- a/tapeout/src/test/scala/transforms/macros/SplitDepth.scala +++ b/tapeout/src/test/scala/transforms/macros/SplitDepth.scala @@ -217,3 +217,59 @@ circuit name_of_sram_module : compile(mem, Some(lib), v, false) execute(Some(mem), Some(lib), false, output) } + + +class SplitDepth2048x8_mrw_Sleep extends MacroCompilerSpec { + val mem = new File(macroDir, "mem-2048x8-mrw.json") + val lib = new File(macroDir, "lib-1024x8-sleep.json") + val v = new File(testDir, "split_depth_2048x8_sleep.v") + val output = +""" +circuit name_of_sram_module : + module name_of_sram_module : + input clock : Clock + input RW0A : UInt<11> + input RW0I : UInt<8> + output RW0O : UInt<8> + input RW0E : UInt<1> + input RW0W : UInt<1> + input RW0M : UInt<1> + + node RW0A_sel = bits(RW0A, 10, 10) + inst mem_0_0 of vendor_sram + mem_0_0.sleep <= UInt<1>("h0") + mem_0_0.clock <= clock + mem_0_0.RW0A <= RW0A + node RW0O_0_0 = bits(mem_0_0.RW0O, 7, 0) + mem_0_0.RW0I <= bits(RW0I, 7, 0) + mem_0_0.RW0M <= bits(RW0M, 0, 0) + mem_0_0.RW0W <= and(RW0W, eq(RW0A_sel, UInt<1>("h0"))) + mem_0_0.RW0E <= and(RW0E, eq(RW0A_sel, UInt<1>("h0"))) + node RW0O_0 = RW0O_0_0 + inst mem_1_0 of vendor_sram + mem_1_0.sleep <= UInt<1>("h0") + mem_1_0.clock <= clock + mem_1_0.RW0A <= RW0A + node RW0O_1_0 = bits(mem_1_0.RW0O, 7, 0) + mem_1_0.RW0I <= bits(RW0I, 7, 0) + mem_1_0.RW0M <= bits(RW0M, 0, 0) + mem_1_0.RW0W <= and(RW0W, eq(RW0A_sel, UInt<1>("h1"))) + mem_1_0.RW0E <= and(RW0E, eq(RW0A_sel, UInt<1>("h1"))) + node RW0O_1 = RW0O_1_0 + RW0O <= mux(eq(RW0A_sel, UInt<1>("h0")), RW0O_0, mux(eq(RW0A_sel, UInt<1>("h1")), RW0O_1, UInt<1>("h0"))) + + extmodule vendor_sram : + input clock : Clock + input RW0A : UInt<10> + input RW0I : UInt<8> + output RW0O : UInt<8> + input RW0E : UInt<1> + input RW0W : UInt<1> + input RW0M : UInt<1> + input sleep : UInt<1> + + defname = vendor_sram +""" + compile(mem, Some(lib), v, false) + execute(Some(mem), Some(lib), false, output) +}