connect extra ports

2017-07-04 17:15:38 -07:00
parent 98155dd831
commit 4f5a9ae02e
4 changed files with 113 additions and 6 deletions
--- a/tapeout/src/main/scala/transforms/macros/MacroCompiler.scala
+++ b/tapeout/src/main/scala/transforms/macros/MacroCompiler.scala
@@ -92,7 +92,12 @@ class MacroCompilerPass(memFile: Option[File],
    }
    for ((off, i) <- (0 until mem.depth.toInt by lib.depth.toInt).zipWithIndex) {
      for (j <- pairs.indices) {
-        stmts += WDefInstance(NoInfo, s"mem_${i}_${j}", lib.name, instType)
+        val name = s"mem_${i}_${j}"
+        stmts += WDefInstance(NoInfo, name, lib.name, instType)
+        // connect extra ports
+        stmts ++= lib.extraPorts map { case (portName, portValue) =>
+          Connect(NoInfo, WSubField(WRef(name), portName), portValue)
+        }
      }
      for ((memPort, libPort) <- pairedPorts) {
        val addrMatch = selects get memPort.addressName match {