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connect extra ports

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This commit is contained in:
Donggyu Kim
2017-07-04 17:15:38 -07:00
committed by edwardcwang
parent 98155dd831
commit 4f5a9ae02e
4 changed files with 113 additions and 6 deletions
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7
tapeout/src/main/scala/transforms/macros/MacroCompiler.scala
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@@ -92,7 +92,12 @@ class MacroCompilerPass(memFile: Option[File],
}
for ((off, i) <- (0 until mem.depth.toInt by lib.depth.toInt).zipWithIndex) {
for (j <- pairs.indices) {
stmts += WDefInstance(NoInfo, s"mem_${i}_${j}", lib.name, instType)
val name = s"mem_${i}_${j}"
stmts += WDefInstance(NoInfo, name, lib.name, instType)
// connect extra ports
stmts ++= lib.extraPorts map { case (portName, portValue) =>
Connect(NoInfo, WSubField(WRef(name), portName), portValue)
}
}
for ((memPort, libPort) <- pairedPorts) {
val addrMatch = selects get memPort.addressName match {

21
tapeout/src/main/scala/transforms/macros/Utils.scala
View File

@@ -67,8 +67,8 @@ case class MacroPort(
class Macro(lib: Map[String, Any]) {
val name = lib("name").asInstanceOf[String]
val width = BigInt(lib("width").asInstanceOf[Double].toInt)
val depth = BigInt(lib("depth").asInstanceOf[Double].toInt)
val width = BigInt(lib("width").asInstanceOf[Double].toLong)
val depth = BigInt(lib("depth").asInstanceOf[Double].toLong)
val ports = lib("ports").asInstanceOf[List[_]] map { x =>
val map = x.asInstanceOf[Map[String, Any]]
MacroPort(
@@ -88,15 +88,26 @@ class Macro(lib: Map[String, Any]) {
map get "write enable port polarity",
map get "mask port name" map (_.asInstanceOf[String]),
map get "mask port polarity",
map get "mask granularity" map (x => BigInt(x.asInstanceOf[Double].toInt)),
map get "mask granularity" map (x => BigInt(x.asInstanceOf[Double].toLong)),
width,
depth
)
}
private val modPorts = ports flatMap (_.ports)
val extraPorts = lib get "extra ports" match {
case None => Nil
case Some(p) => p.asInstanceOf[List[_]] map { x =>
val map = x.asInstanceOf[Map[String, Any]]
assert(map("type").asInstanceOf[String] == "constant") // TODO: release it?
val name = map("name").asInstanceOf[String]
val width = BigInt(map("width").asInstanceOf[Double].toLong)
val value = BigInt(map("value").asInstanceOf[Double].toLong)
(name -> UIntLiteral(value, IntWidth(width)))
}
}
private val modPorts = (ports flatMap (_.ports)) ++
(extraPorts map { case (name, value) => Port(NoInfo, name, Input, value.tpe) })
val blackbox = ExtModule(NoInfo, name, modPorts, name, Nil)
def module(body: Statement) = Module(NoInfo, name, modPorts, body)
}
object Utils {