[skip CI] Update docs/VLSI/Tutorial.rst

2021-06-10 13:34:07 -07:00
parent 120c096962
commit 4e9c951ad2
1 changed files with 1 additions and 1 deletions
--- a/docs/VLSI/Tutorial.rst
+++ b/docs/VLSI/Tutorial.rst
@@ -157,7 +157,7 @@ Post-synthesis and post-P&R simulations use the ``sim-syn`` and ``sim-par`` targ

 There are also ``-debug`` and ``-debug-timing``, which will instruct VCS to write a SAIF + VPD and do timing-annotated simulations, respectively. See the ``sim.mk`` file for all available targets.

-Note that for the ASAP7 example, gate-level simulations will timeout (the cause is being investigated).
+Note that for the ASAP7 example, gate-level simulations will currently timeout.

 Power/Rail Analysis
 ^^^^^^^^^^^^^^^^^^^