From 4e9c951ad27c342097a0ad4f76722a2aedbbbcdd Mon Sep 17 00:00:00 2001 From: alonamid Date: Thu, 10 Jun 2021 13:34:07 -0700 Subject: [PATCH] [skip CI] Update docs/VLSI/Tutorial.rst --- docs/VLSI/Tutorial.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/VLSI/Tutorial.rst b/docs/VLSI/Tutorial.rst index f522da8a..38eee0b5 100644 --- a/docs/VLSI/Tutorial.rst +++ b/docs/VLSI/Tutorial.rst @@ -157,7 +157,7 @@ Post-synthesis and post-P&R simulations use the ``sim-syn`` and ``sim-par`` targ There are also ``-debug`` and ``-debug-timing``, which will instruct VCS to write a SAIF + VPD and do timing-annotated simulations, respectively. See the ``sim.mk`` file for all available targets. -Note that for the ASAP7 example, gate-level simulations will timeout (the cause is being investigated). +Note that for the ASAP7 example, gate-level simulations will currently timeout. Power/Rail Analysis ^^^^^^^^^^^^^^^^^^^