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Fix MacroCompiler for CE-less Library Memories

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If a memory doesn't have a mask and doesn't have a chip enable, make sure that you use the `mem` chip enable to connect to the `we` port on the `lib` memory. Fixes a bug where the `lib` `we` signal would be tied to the `mem` `wmode` signal but then the macro would have no `en` signal connected to it.
This commit is contained in:
Abraham Gonzalez
2019-11-05 14:04:31 -08:00
committed by GitHub
parent 8b0ef4d770
commit 46e2ecb9ae
1 changed files with 6 additions and 3 deletions
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9
macros/src/main/scala/MacroCompiler.scala
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@@ -517,13 +517,16 @@ class MacroCompilerPass(mems: Option[Seq[Macro]],
/* Palmer: If we're expected to provide mask ports without a /* Palmer: If we're expected to provide mask ports without a
* memory that actually has them then we can use the * memory that actually has them then we can use the
* write enable port instead of the mask port. */ * write enable port instead of the mask port. */
stmts += connectPorts(andAddrMatch(and(memWriteEnable, memMask)),
we, we_polarity)
chipEnable match { chipEnable match {
case Some(PolarizedPort(en, en_polarity)) => { case Some(PolarizedPort(en, en_polarity)) => {
stmts += connectPorts(andAddrMatch(and(memWriteEnable, memMask)),
we, we_polarity)
stmts += connectPorts(andAddrMatch(memChipEnable), en, en_polarity) stmts += connectPorts(andAddrMatch(memChipEnable), en, en_polarity)
} }
case _ => // TODO: do we care about the case where mem has chipEnable but lib doesn't? case _ => {
stmts += connectPorts(andAddrMatch(and(and(memWriteEnable, memChipEnable), memMask)),
we, we_polarity)
}
} }
} else { } else {
System.err.println("cannot emulate multi-bit mask ports with write enable") System.err.println("cannot emulate multi-bit mask ports with write enable")