From 46e2ecb9ae79f32ea864a3de5648586dab794434 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Tue, 5 Nov 2019 14:04:31 -0800 Subject: [PATCH] Fix MacroCompiler for CE-less Library Memories If a memory doesn't have a mask and doesn't have a chip enable, make sure that you use the `mem` chip enable to connect to the `we` port on the `lib` memory. Fixes a bug where the `lib` `we` signal would be tied to the `mem` `wmode` signal but then the macro would have no `en` signal connected to it. --- macros/src/main/scala/MacroCompiler.scala | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/macros/src/main/scala/MacroCompiler.scala b/macros/src/main/scala/MacroCompiler.scala index 9e94bdb9..c51e7845 100644 --- a/macros/src/main/scala/MacroCompiler.scala +++ b/macros/src/main/scala/MacroCompiler.scala @@ -517,13 +517,16 @@ class MacroCompilerPass(mems: Option[Seq[Macro]], /* Palmer: If we're expected to provide mask ports without a * memory that actually has them then we can use the * write enable port instead of the mask port. */ - stmts += connectPorts(andAddrMatch(and(memWriteEnable, memMask)), - we, we_polarity) chipEnable match { case Some(PolarizedPort(en, en_polarity)) => { + stmts += connectPorts(andAddrMatch(and(memWriteEnable, memMask)), + we, we_polarity) stmts += connectPorts(andAddrMatch(memChipEnable), en, en_polarity) } - case _ => // TODO: do we care about the case where mem has chipEnable but lib doesn't? + case _ => { + stmts += connectPorts(andAddrMatch(and(and(memWriteEnable, memChipEnable), memMask)), + we, we_polarity) + } } } else { System.err.println("cannot emulate multi-bit mask ports with write enable")