43f6083b69
Cores now have an extra CoreParam, useSupervisor which was set to the default false. Whether a core has supervisor mode is the union of this and useVM which defaults true so not change was made by this addition. BusTopologies are now set with the Config system rather than a system mixin and so all configs now include the config most similar to the previous mixin Testchipip was updated to be able to replace the systembus, in this new config system, with a ring bus. The L2 cache repo needed a similar update on how to find the buses. It currently points to the ucb-bar fork Treadle is bumped to its release branch
171 lines
8.4 KiB
Scala
171 lines
8.4 KiB
Scala
package chipyard
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import freechips.rocketchip.config.{Config}
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// ---------------------
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// Heterogenous Configs
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// ---------------------
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class LargeBoomAndRocketConfig extends Config(
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new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter
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new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts
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new chipyard.iobinders.WithBlackBoxSimMem ++ // drive the master AXI4 memory with a SimAXIMem
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new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing)
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new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing
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new testchipip.WithTSI ++ // use testchipip serial offchip link
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new chipyard.config.WithBootROM ++ // use default bootrom
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new chipyard.config.WithUART ++ // add a UART
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new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs
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new chipyard.config.WithRenumberHarts ++ // avoid hartid overlap
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new boom.common.WithLargeBooms ++ // 3-wide boom
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new boom.common.WithNBoomCores(1) ++ // single-core boom
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new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip)
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new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip)
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new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache
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new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core
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new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2
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new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system
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// DOC include start: BoomAndRocketWithHwacha
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class HwachaLargeBoomAndHwachaRocketConfig extends Config(
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new chipyard.iobinders.WithUARTAdapter ++
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new chipyard.iobinders.WithTieOffInterrupts ++
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new chipyard.iobinders.WithBlackBoxSimMem ++
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new chipyard.iobinders.WithTiedOffDebug ++
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new chipyard.iobinders.WithSimSerial ++
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new testchipip.WithTSI ++
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new chipyard.config.WithBootROM ++
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new chipyard.config.WithUART ++
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new chipyard.config.WithL2TLBs(1024) ++
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new hwacha.DefaultHwachaConfig ++ // add hwacha to all harts
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new chipyard.config.WithRenumberHarts ++
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new boom.common.WithLargeBooms ++
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new boom.common.WithNBoomCores(1) ++
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new freechips.rocketchip.subsystem.WithNoMMIOPort ++
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new freechips.rocketchip.subsystem.WithNoSlavePort ++
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new freechips.rocketchip.subsystem.WithInclusiveCache ++
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new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
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new freechips.rocketchip.system.BaseConfig)
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// DOC include end: BoomAndRocketWithHwacha
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class DualLargeBoomAndRocketConfig extends Config(
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new chipyard.iobinders.WithUARTAdapter ++
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new chipyard.iobinders.WithTieOffInterrupts ++
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new chipyard.iobinders.WithBlackBoxSimMem ++
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new chipyard.iobinders.WithTiedOffDebug ++
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new chipyard.iobinders.WithSimSerial ++
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new testchipip.WithTSI ++
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new chipyard.config.WithBootROM ++
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new chipyard.config.WithUART ++
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new chipyard.config.WithL2TLBs(1024) ++
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new chipyard.config.WithRenumberHarts ++
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new boom.common.WithLargeBooms ++
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new boom.common.WithNBoomCores(2) ++ // 2 boom cores
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new freechips.rocketchip.subsystem.WithNoMMIOPort ++
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new freechips.rocketchip.subsystem.WithNoSlavePort ++
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new freechips.rocketchip.subsystem.WithInclusiveCache ++
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new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
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new freechips.rocketchip.system.BaseConfig)
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// DOC include start: DualBoomAndRocketOneHwacha
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class LargeBoomAndHwachaRocketConfig extends Config(
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new chipyard.iobinders.WithUARTAdapter ++
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new chipyard.iobinders.WithTieOffInterrupts ++
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new chipyard.iobinders.WithBlackBoxSimMem ++
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new chipyard.iobinders.WithTiedOffDebug ++
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new chipyard.iobinders.WithSimSerial ++
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new testchipip.WithTSI ++
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new chipyard.config.WithBootROM ++
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new chipyard.config.WithUART ++
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new chipyard.config.WithMultiRoCC ++ // support heterogeneous rocc
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new chipyard.config.WithMultiRoCCHwacha(1) ++ // put hwacha on hart-2 (rocket)
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new chipyard.config.WithL2TLBs(1024) ++
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new chipyard.config.WithRenumberHarts ++
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new boom.common.WithLargeBooms ++
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new boom.common.WithNBoomCores(1) ++
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new freechips.rocketchip.subsystem.WithNoMMIOPort ++
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new freechips.rocketchip.subsystem.WithNoSlavePort ++
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new freechips.rocketchip.subsystem.WithInclusiveCache ++
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new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
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new freechips.rocketchip.system.BaseConfig)
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// DOC include end: DualBoomAndRocketOneHwacha
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class LargeBoomAndRV32RocketConfig extends Config(
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new chipyard.iobinders.WithUARTAdapter ++
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new chipyard.iobinders.WithTieOffInterrupts ++
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new chipyard.iobinders.WithBlackBoxSimMem ++
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new chipyard.iobinders.WithTiedOffDebug ++
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new chipyard.iobinders.WithSimSerial ++
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new testchipip.WithTSI ++
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new chipyard.config.WithBootROM ++
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new chipyard.config.WithUART ++
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new chipyard.config.WithL2TLBs(1024) ++
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new chipyard.config.WithRenumberHarts ++
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new boom.common.WithLargeBooms ++
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new boom.common.WithNBoomCores(1) ++
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new freechips.rocketchip.subsystem.WithNoMMIOPort ++
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new freechips.rocketchip.subsystem.WithNoSlavePort ++
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new freechips.rocketchip.subsystem.WithInclusiveCache ++
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new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
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new freechips.rocketchip.subsystem.WithRV32 ++ // set RocketTiles to be 32-bit
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
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new freechips.rocketchip.system.BaseConfig)
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// DOC include start: DualBoomAndRocket
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class DualLargeBoomAndDualRocketConfig extends Config(
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new chipyard.iobinders.WithUARTAdapter ++
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new chipyard.iobinders.WithTieOffInterrupts ++
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new chipyard.iobinders.WithBlackBoxSimMem ++
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new chipyard.iobinders.WithTiedOffDebug ++
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new chipyard.iobinders.WithSimSerial ++
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new testchipip.WithTSI ++
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new chipyard.config.WithBootROM ++
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new chipyard.config.WithUART ++
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new chipyard.config.WithL2TLBs(1024) ++
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new chipyard.config.WithRenumberHarts ++
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new boom.common.WithLargeBooms ++
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new boom.common.WithNBoomCores(2) ++ // 2 boom cores
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new freechips.rocketchip.subsystem.WithNoMMIOPort ++
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new freechips.rocketchip.subsystem.WithNoSlavePort ++
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new freechips.rocketchip.subsystem.WithInclusiveCache ++
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new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
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new freechips.rocketchip.subsystem.WithNBigCores(2) ++ // 2 rocket cores
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new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
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new freechips.rocketchip.system.BaseConfig)
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// DOC include end: DualBoomAndRocket
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class LargeBoomAndRocketWithControlCoreConfig extends Config(
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new chipyard.iobinders.WithUARTAdapter ++
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new chipyard.iobinders.WithTieOffInterrupts ++
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new chipyard.iobinders.WithBlackBoxSimMem ++
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new chipyard.iobinders.WithTiedOffDebug ++
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new chipyard.iobinders.WithSimSerial ++
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new testchipip.WithTSI ++
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new chipyard.config.WithBootROM ++
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new chipyard.config.WithUART ++
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new chipyard.config.WithControlCore ++ // add small control core to last hartid
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new chipyard.config.WithL2TLBs(1024) ++
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new chipyard.config.WithRenumberHarts ++
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new boom.common.WithLargeBooms ++
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new boom.common.WithNBoomCores(1) ++
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new freechips.rocketchip.subsystem.WithNoMMIOPort ++
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new freechips.rocketchip.subsystem.WithNoSlavePort ++
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new freechips.rocketchip.subsystem.WithInclusiveCache ++
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new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
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new freechips.rocketchip.system.BaseConfig)
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