182 lines
9.5 KiB
Scala
182 lines
9.5 KiB
Scala
package chipyard
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import chipyard.config.{AbstractConfig, WithBootROM}
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import chipyard.stage.phases.TargetDirKey
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import org.chipsalliance.cde.config.{Config, Field}
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import freechips.rocketchip.diplomacy.AsynchronousCrossing
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import freechips.rocketchip.devices.tilelink.{BootROMLocated, RadianceROMParams, RadianceROMsLocated}
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import freechips.rocketchip.subsystem.{WithBootROMFile, WithExtMemSize}
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import freechips.rocketchip.tile.XLen
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// --------------
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// Rocket Configs
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// --------------
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class RocketConfig extends Config(
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core
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new chipyard.config.AbstractConfig)
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class WithRadROMs(address: BigInt, size: Int, filename: String) extends Config((site, here, up) => {
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case RadianceROMsLocated() => up(RadianceROMsLocated()) ++
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Seq(RadianceROMParams(
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address = address,
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size = size,
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contentFileName = filename
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))
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})
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class WithRadBootROM(address: BigInt = 0x10000, size: Int = 0x10000, hang: BigInt = 0x10100) extends Config((site, here, up) => {
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case BootROMLocated(x) => up(BootROMLocated(x), site)
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.map(_.copy(
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address = address,
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size = size,
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hang = hang,
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contentFileName = s"${site(TargetDirKey)}/bootrom.radiance.rv${site(XLen)}.img"
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))
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})
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class RadianceROMConfig extends Config(
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new freechips.rocketchip.subsystem.WithRadianceCores() ++
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new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
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new WithExtMemSize(BigInt("80000000", 16)) ++
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new WithRadBootROM() ++
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new WithRadROMs(0x7FFF0000L, 0x10000, "sims/vcs/args.bin") ++
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new WithRadROMs(0x20000L, 0x8000, "sims/vcs/op_a.bin") ++
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new WithRadROMs(0x28000L, 0x8000, "sims/vcs/op_b.bin") ++
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new AbstractConfig)
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class RadianceConfig extends Config(
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new freechips.rocketchip.subsystem.WithRadianceCores() ++
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new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
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new WithExtMemSize(BigInt("80000000", 16)) ++
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new WithRadBootROM() ++
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new testchipip.WithMbusScratchpad(base=0x7FFF0000L, size=0x10000, banks=1) ++
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new AbstractConfig)
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class TinyRocketConfig extends Config(
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new chipyard.iobinders.WithDontTouchIOBinders(false) ++ // TODO FIX: Don't dontTouch the ports
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new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++ // use incoherent bus topology
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new freechips.rocketchip.subsystem.WithNBanks(0) ++ // remove L2$
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new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove backing memory
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new freechips.rocketchip.subsystem.With1TinyCore ++ // single tiny rocket-core
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new chipyard.config.AbstractConfig)
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class RocketGPUConfig extends Config(
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new freechips.rocketchip.subsystem.WithNCustomSmallCores(2) ++ // multiple rocket-core
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new chipyard.config.AbstractConfig)
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class SimAXIRocketConfig extends Config(
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new chipyard.harness.WithSimAXIMem ++ // drive the master AXI4 memory with a SimAXIMem, a 1-cycle magic memory, instead of default SimDRAM
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new chipyard.config.AbstractConfig)
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class QuadRocketConfig extends Config(
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new freechips.rocketchip.subsystem.WithNBigCores(4) ++ // quad-core (4 RocketTiles)
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new chipyard.config.AbstractConfig)
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class Cloned64RocketConfig extends Config(
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new freechips.rocketchip.subsystem.WithCloneRocketTiles(63, 0) ++ // copy tile0 63 more times
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // tile0 is a BigRocket
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new chipyard.config.AbstractConfig)
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class RV32RocketConfig extends Config(
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new freechips.rocketchip.subsystem.WithRV32 ++ // set RocketTiles to be 32-bit
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new chipyard.config.AbstractConfig)
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class GB1MemoryRocketConfig extends Config(
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new freechips.rocketchip.subsystem.WithExtMemSize((1<<30) * 1L) ++ // use 1GB simulated external memory
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new chipyard.config.AbstractConfig)
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// DOC include start: l1scratchpadrocket
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class ScratchpadOnlyRocketConfig extends Config(
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new chipyard.config.WithL2TLBs(0) ++
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new freechips.rocketchip.subsystem.WithNBanks(0) ++
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new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove offchip mem port
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new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 DCache scratchpad as base phys mem
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new chipyard.config.AbstractConfig)
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// DOC include end: l1scratchpadrocket
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class MMIOScratchpadOnlyRocketConfig extends Config(
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new freechips.rocketchip.subsystem.WithDefaultMMIOPort ++ // add default external master port
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new freechips.rocketchip.subsystem.WithDefaultSlavePort ++ // add default external slave port
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new ScratchpadOnlyRocketConfig
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)
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class L1ScratchpadRocketConfig extends Config(
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new chipyard.config.WithRocketICacheScratchpad ++ // use rocket ICache scratchpad
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new chipyard.config.WithRocketDCacheScratchpad ++ // use rocket DCache scratchpad
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new chipyard.config.AbstractConfig)
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// DOC include start: mbusscratchpadrocket
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class MbusScratchpadOnlyRocketConfig extends Config(
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new testchipip.WithMbusScratchpad(banks=2, partitions=2) ++ // add 2 partitions of 2 banks mbus backing scratchpad
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new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove offchip mem port
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new chipyard.config.AbstractConfig)
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// DOC include end: mbusscratchpadrocket
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class SbusScratchpadRocketConfig extends Config(
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new testchipip.WithSbusScratchpad(base=0x70000000L, banks=4) ++ // add 4 banks sbus backing scratchpad
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new chipyard.config.AbstractConfig)
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class MulticlockRocketConfig extends Config(
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new freechips.rocketchip.subsystem.WithAsynchronousRocketTiles(3, 3) ++ // Add async crossings between RocketTile and uncore
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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// Frequency specifications
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new chipyard.config.WithTileFrequency(1000.0) ++ // Matches the maximum frequency of U540
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new chipyard.clocking.WithClockGroupsCombinedByName(("uncore" , Seq("sbus", "cbus", "implicit"), Nil),
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("periphery", Seq("pbus", "fbus"), Nil)) ++
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new chipyard.config.WithSystemBusFrequency(500.0) ++ // Matches the maximum frequency of U540
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new chipyard.config.WithMemoryBusFrequency(500.0) ++ // Matches the maximum frequency of U540
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new chipyard.config.WithPeripheryBusFrequency(500.0) ++ // Matches the maximum frequency of U540
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// Crossing specifications
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new chipyard.config.WithFbusToSbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between FBUS and SBUS
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new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS
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new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS
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new testchipip.WithAsynchronousSerialSlaveCrossing ++ // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS
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new chipyard.config.AbstractConfig)
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// DOC include start: MulticlockAXIOverSerialConfig
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class MulticlockAXIOverSerialConfig extends Config(
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new chipyard.config.WithSystemBusFrequency(250) ++
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new chipyard.config.WithPeripheryBusFrequency(250) ++
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new chipyard.config.WithMemoryBusFrequency(250) ++
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new chipyard.config.WithFrontBusFrequency(50) ++
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new chipyard.config.WithTileFrequency(500, Some(1)) ++
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new chipyard.config.WithTileFrequency(250, Some(0)) ++
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new chipyard.config.WithFbusToSbusCrossingType(AsynchronousCrossing()) ++
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new testchipip.WithAsynchronousSerialSlaveCrossing ++
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new freechips.rocketchip.subsystem.WithAsynchronousRocketTiles(
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AsynchronousCrossing().depth,
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AsynchronousCrossing().sourceSync) ++
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new chipyard.harness.WithSimAXIMemOverSerialTL ++ // add SimDRAM DRAM model for axi4 backing memory over the SerDes link, if axi4 mem is enabled
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new testchipip.WithSerialTLBackingMemory ++ // remove axi4 mem port in favor of SerialTL memory
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new freechips.rocketchip.subsystem.WithNBigCores(2) ++
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new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ // 1 memory channel
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new chipyard.config.AbstractConfig)
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// DOC include end: MulticlockAXIOverSerialConfig
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class CustomIOChipTopRocketConfig extends Config(
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new chipyard.example.WithCustomChipTop ++
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new chipyard.example.WithCustomIOCells ++
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core
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new chipyard.config.AbstractConfig)
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class PrefetchingRocketConfig extends Config(
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new barf.WithHellaCachePrefetcher(Seq(0), barf.SingleStridedPrefetcherParams()) ++ // strided prefetcher, sits in front of the L1D$, monitors core requests to prefetching into the L1D$
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new barf.WithTLICachePrefetcher(barf.MultiNextLinePrefetcherParams()) ++ // next-line prefetcher, sits between L1I$ and L2, monitors L1I$ misses to prefetch into L2
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new barf.WithTLDCachePrefetcher(barf.SingleAMPMPrefetcherParams()) ++ // AMPM prefetcher, sits between L1D$ and L2, monitors L1D$ misses to prefetch into L2
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new chipyard.config.WithTilePrefetchers ++ // add TL prefetchers between tiles and the sbus
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new freechips.rocketchip.subsystem.WithNonblockingL1(2) ++ // non-blocking L1D$, L1 prefetching only works with non-blocking L1D$
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core
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new chipyard.config.AbstractConfig)
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