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Merge branch 'main' into clock_tap

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This commit is contained in:
Jerry Zhao
2023-12-16 16:56:10 -08:00
committed by GitHub
parent 2e77867577 a181790649
commit 2f1012294d
35 changed files with 211 additions and 104 deletions
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25
generators/chipyard/src/main/resources/csrc/spiketile.cc
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@@ -447,18 +447,6 @@ chipyard_simif_t::chipyard_simif_t(size_t icache_ways,
use_stq(false),
htif(nullptr),
fast_clint(false),
cfg(std::make_pair(0, 0),
nullptr,
isastr,
"MSU",
"vlen:128,elen:64",
false,
endianness_little,
pmpregions,
std::vector<mem_cfg_t>(),
std::vector<size_t>(),
false,
0),
accessed_tofrom_host(false),
icache_ways(icache_ways),
icache_sets(icache_sets),
@@ -470,6 +458,19 @@ chipyard_simif_t::chipyard_simif_t(size_t icache_ways,
mmio_inflight(false)
{
cfg.initrd_bounds = std::make_pair(0, 0);
cfg.bootargs = nullptr;
cfg.isa = isastr;
cfg.priv = "MSU";
cfg.varch = "vlen:128,elen:64";
cfg.misaligned = false;
cfg.endianness = endianness_little;
cfg.pmpregions = pmpregions;
cfg.mem_layout = std::vector<mem_cfg_t>();
cfg.hartids = std::vector<size_t>();
cfg.explicit_hartids = false;
cfg.trigger_count = 0;
icache.resize(icache_ways);
for (auto &w : icache) {
w.resize(icache_sets);

2
generators/chipyard/src/main/scala/Subsystem.scala
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@@ -29,7 +29,7 @@ import testchipip.{CanHavePeripheryTLSerial, SerialTLKey}
trait CanHaveHTIF { this: BaseSubsystem =>
// Advertise HTIF if system can communicate with fesvr
if (this match {
case _: CanHavePeripheryTLSerial if p(SerialTLKey).nonEmpty => true
case _: CanHavePeripheryTLSerial if (p(SerialTLKey).size != 0) => true
case _: HasPeripheryDebug if (!p(DebugModuleKey).isEmpty && p(ExportDebug).dmi) => true
case _ => false
}) {

13
generators/chipyard/src/main/scala/config/AbstractConfig.scala
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@@ -54,15 +54,20 @@ class AbstractConfig extends Config(
new chipyard.clocking.WithClockTapIOCells ++ // Default generate a clock tapio
new chipyard.clocking.WithPassthroughClockGenerator ++ // Default punch out IOs to the Harness
new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", // Default merge all the bus clocks
Seq("sbus", "mbus", "pbus", "fbus", "cbus", "implicit"), Seq("tile"))) ++
Seq("sbus", "mbus", "pbus", "fbus", "cbus", "obus", "implicit"), Seq("tile"))) ++
new chipyard.config.WithPeripheryBusFrequency(500.0) ++ // Default 500 MHz pbus
new chipyard.config.WithMemoryBusFrequency(500.0) ++ // Default 500 MHz mbus
new chipyard.config.WithControlBusFrequency(500.0) ++ // Default 500 MHz cbus
new chipyard.config.WithSystemBusFrequency(500.0) ++ // Default 500 MHz sbus
new chipyard.config.WithFrontBusFrequency(500.0) ++ // Default 500 MHz fbus
new chipyard.config.WithOffchipBusFrequency(500.0) ++ // Default 500 MHz obus
new testchipip.WithCustomBootPin ++ // add a custom-boot-pin to support pin-driven boot address
new testchipip.WithBootAddrReg ++ // add a boot-addr-reg for configurable boot address
new testchipip.WithSerialTLClientIdBits(4) ++ // support up to 1 << 4 simultaneous requests from serialTL port
new testchipip.WithSerialTLWidth(32) ++ // fatten the serialTL interface to improve testing performance
new testchipip.WithDefaultSerialTL ++ // use serialized tilelink port to external serialadapter/harnessRAM
new testchipip.WithSerialTL(Seq(testchipip.SerialTLParams( // add a serial-tilelink interface
client = Some(testchipip.SerialTLClientParams(idBits = 4)), // serial-tilelink interface will master the FBUS, and support 4 idBits
width = 32 // serial-tilelink interface with 32 lanes
))) ++
new chipyard.config.WithDebugModuleAbstractDataWords(8) ++ // increase debug module data capacity
new chipyard.config.WithBootROM ++ // use default bootrom
new chipyard.config.WithUART ++ // add a UART

7
generators/chipyard/src/main/scala/config/ChipConfigs.scala
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@@ -23,8 +23,8 @@ class ChipLikeRocketConfig extends Config(
// Set up I/O
//==================================
new testchipip.WithSerialTLWidth(4) ++ // 4bit wide Serialized TL interface to minimize IO
new testchipip.WithSerialTLBackingMemory ++ // Configure the off-chip memory accessible over serial-tl as backing memory
new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 4L) ++ // 4GB max external memory
new testchipip.WithSerialTLMem(size = (1 << 30) * 4L) ++ // Configure the off-chip memory accessible over serial-tl as backing memory
new freechips.rocketchip.subsystem.WithNoMemPort ++ // Remove axi4 mem port
new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ // 1 memory channel
//==================================
@@ -89,6 +89,9 @@ class ChipBringupHostConfig extends Config(
new chipyard.config.WithFrontBusFrequency(75.0) ++ // run all buses of this system at 75 MHz
new chipyard.config.WithMemoryBusFrequency(75.0) ++
new chipyard.config.WithPeripheryBusFrequency(75.0) ++
new chipyard.config.WithSystemBusFrequency(75.0) ++
new chipyard.config.WithControlBusFrequency(75.0) ++
new chipyard.config.WithOffchipBusFrequency(75.0) ++
// Base is the no-cores config
new chipyard.NoCoresConfig)

92
generators/chipyard/src/main/scala/config/NoCConfigs.scala
View File

@@ -6,6 +6,7 @@ import freechips.rocketchip.subsystem.{SBUS, MBUS}
import constellation.channel._
import constellation.routing._
import constellation.router._
import constellation.topology._
import constellation.noc._
import constellation.soc.{GlobalNoCParams}
@@ -45,7 +46,7 @@ import scala.collection.immutable.ListMap
* | SI:Core 2 | SO:system[0] | SO:system[1] | SI:Core 3 |
* |(0)___________|(1)___________|(2)___________|(3)___________|
* | FBus | Core 0 | Core 1 | Pbus |
* | SI:serial-tl | SI:Core 0 | SI:Core 1 | SO:pbus |
* | SI:serial_tl | SI:Core 0 | SI:Core 1 | SO:pbus |
* |______________|______________|______________|______________|
*
* |(0)___________|(1)___________|(2)___________|(3)___________|
@@ -62,37 +63,37 @@ import scala.collection.immutable.ListMap
*/
// DOC include start: MultiNoCConfig
class MultiNoCConfig extends Config(
new constellation.soc.WithCbusNoC(constellation.protocol.TLNoCParams(
new constellation.soc.WithCbusNoC(constellation.protocol.SimpleTLNoCParams(
constellation.protocol.DiplomaticNetworkNodeMapping(
inNodeMapping = ListMap(
"serial-tl" -> 0),
"serial_tl" -> 0),
outNodeMapping = ListMap(
"error" -> 1, "l2[0]" -> 2, "pbus" -> 3, "plic" -> 4,
"error" -> 1, "ctrls[0]" -> 2, "pbus" -> 3, "plic" -> 4,
"clint" -> 5, "dmInner" -> 6, "bootrom" -> 7, "clock" -> 8)),
NoCParams(
topology = TerminalRouter(BidirectionalLine(9)),
channelParamGen = (a, b) => UserChannelParams(Seq.fill(5) { UserVirtualChannelParams(4) }),
routingRelation = NonblockingVirtualSubnetworksRouting(TerminalRouterRouting(BidirectionalLineRouting()), 5, 1))
)) ++
new constellation.soc.WithMbusNoC(constellation.protocol.TLNoCParams(
new constellation.soc.WithMbusNoC(constellation.protocol.SimpleTLNoCParams(
constellation.protocol.DiplomaticNetworkNodeMapping(
inNodeMapping = ListMap(
"L2 InclusiveCache[0]" -> 1, "L2 InclusiveCache[1]" -> 2,
"L2 InclusiveCache[2]" -> 5, "L2 InclusiveCache[3]" -> 6),
outNodeMapping = ListMap(
"system[0]" -> 0, "system[1]" -> 3, "system[2]" -> 4 , "system[3]" -> 7,
"serdesser" -> 0)),
"serial_tl_0" -> 0)),
NoCParams(
topology = TerminalRouter(BidirectionalTorus1D(8)),
channelParamGen = (a, b) => UserChannelParams(Seq.fill(10) { UserVirtualChannelParams(4) }),
routingRelation = BlockingVirtualSubnetworksRouting(TerminalRouterRouting(BidirectionalTorus1DShortestRouting()), 5, 2))
)) ++
new constellation.soc.WithSbusNoC(constellation.protocol.TLNoCParams(
new constellation.soc.WithSbusNoC(constellation.protocol.SimpleTLNoCParams(
constellation.protocol.DiplomaticNetworkNodeMapping(
inNodeMapping = ListMap(
"Core 0" -> 1, "Core 1" -> 2, "Core 2" -> 4 , "Core 3" -> 7,
"Core 4" -> 8, "Core 5" -> 11, "Core 6" -> 13, "Core 7" -> 14,
"serial-tl" -> 0),
"serial_tl" -> 0),
outNodeMapping = ListMap(
"system[0]" -> 5, "system[1]" -> 6, "system[2]" -> 9, "system[3]" -> 10,
"pbus" -> 3)),
@@ -133,7 +134,7 @@ class MultiNoCConfig extends Config(
* Core 6 | SI | Core 6 | 16
* Core 7 | SI | Core 7 | 18
* Core 8 | SI | Core 8 | 19
* fbus | SI | serial-tl | 9
* fbus | SI | serial_tl | 9
* pbus | SO | pbus | 4
* L2 0 | SO | system[0] | 0
* L2 1 | SO | system[1] | 2
@@ -145,7 +146,7 @@ class MultiNoCConfig extends Config(
* L2 3 | MI | Cache[3] | 6
* DRAM 0 | MO | system[0] | 3
* DRAM 1 | MO | system[1] | 5
* extram | MO | serdesser | 9
* extram | MO | serial_tl_0 | 9
*/
// DOC include start: SharedNoCConfig
class SharedNoCConfig extends Config(
@@ -162,24 +163,24 @@ class SharedNoCConfig extends Config(
BidirectionalLineRouting()))), 10, 2)
)
)) ++
new constellation.soc.WithMbusNoC(constellation.protocol.TLNoCParams(
new constellation.soc.WithMbusNoC(constellation.protocol.GlobalTLNoCParams(
constellation.protocol.DiplomaticNetworkNodeMapping(
inNodeMapping = ListMap(
"Cache[0]" -> 0, "Cache[1]" -> 2, "Cache[2]" -> 8, "Cache[3]" -> 6),
outNodeMapping = ListMap(
"system[0]" -> 3, "system[1]" -> 5,
"serdesser" -> 9))
), true) ++
new constellation.soc.WithSbusNoC(constellation.protocol.TLNoCParams(
"serial_tl_0" -> 9))
)) ++
new constellation.soc.WithSbusNoC(constellation.protocol.GlobalTLNoCParams(
constellation.protocol.DiplomaticNetworkNodeMapping(
inNodeMapping = ListMap(
"serial-tl" -> 9, "Core 0" -> 2,
"serial_tl" -> 9, "Core 0" -> 2,
"Core 1" -> 10, "Core 2" -> 11, "Core 3" -> 13, "Core 4" -> 14,
"Core 5" -> 15, "Core 6" -> 16, "Core 7" -> 18, "Core 8" -> 19),
outNodeMapping = ListMap(
"system[0]" -> 0, "system[1]" -> 2, "system[2]" -> 8, "system[3]" -> 6,
"pbus" -> 4))
), true) ++
)) ++
new freechips.rocketchip.subsystem.WithNBigCores(8) ++
new freechips.rocketchip.subsystem.WithNBanks(4) ++
new freechips.rocketchip.subsystem.WithNMemoryChannels(2) ++
@@ -187,8 +188,9 @@ class SharedNoCConfig extends Config(
)
// DOC include end: SharedNoCConfig
// This Config implements a simple ring interconnect for the system bus
class SbusRingNoCConfig extends Config(
new constellation.soc.WithSbusNoC(constellation.protocol.TLNoCParams(
new constellation.soc.WithSbusNoC(constellation.protocol.SplitACDxBETLNoCParams(
constellation.protocol.DiplomaticNetworkNodeMapping(
inNodeMapping = ListMap(
"Core 0" -> 0,
@@ -199,19 +201,67 @@ class SbusRingNoCConfig extends Config(
"Core 5" -> 5,
"Core 6" -> 6,
"Core 7" -> 7,
"serial-tl" -> 8),
"serial_tl" -> 8),
outNodeMapping = ListMap(
"system[0]" -> 9,
"system[1]" -> 10,
"system[2]" -> 11,
"system[3]" -> 12,
"pbus" -> 8)), // TSI is on the pbus, so serial-tl and pbus should be on the same node
NoCParams(
acdNoCParams = NoCParams(
topology = UnidirectionalTorus1D(13),
channelParamGen = (a, b) => UserChannelParams(Seq.fill(10) { UserVirtualChannelParams(4) }),
routingRelation = NonblockingVirtualSubnetworksRouting(UnidirectionalTorus1DDatelineRouting(), 5, 2))
channelParamGen = (a, b) => UserChannelParams(Seq.fill(6) { UserVirtualChannelParams(4) }),
routingRelation = NonblockingVirtualSubnetworksRouting(UnidirectionalTorus1DDatelineRouting(), 3, 2)),
beNoCParams = NoCParams(
topology = UnidirectionalTorus1D(13),
channelParamGen = (a, b) => UserChannelParams(Seq.fill(4) { UserVirtualChannelParams(1) }),
routingRelation = NonblockingVirtualSubnetworksRouting(UnidirectionalTorus1DDatelineRouting(), 2, 2))
)) ++
new freechips.rocketchip.subsystem.WithNBigCores(8) ++
new freechips.rocketchip.subsystem.WithNBanks(4) ++
new chipyard.config.AbstractConfig
)
// This config integrates a mesh interconnect for the system bus, and divides the system bus
// tilelink messages across two isolated interconnects
class SbusMeshNoCConfig extends Config(
new constellation.soc.WithSbusNoC(constellation.protocol.SplitACDxBETLNoCParams(
constellation.protocol.DiplomaticNetworkNodeMapping(
inNodeMapping = ListMap(
"Core 0 " -> 0,
"Core 1 " -> 1,
"Core 2 " -> 2,
"Core 3 " -> 3,
"Core 4 " -> 4,
"Core 5 " -> 7,
"Core 6 " -> 8,
"Core 7 " -> 11,
"Core 8 " -> 12,
"Core 9 " -> 13,
"Core 10 " -> 14,
"Core 11 " -> 15,
"serial-tl" -> 0),
outNodeMapping = ListMap(
"system[0]" -> 5,
"system[1]" -> 6,
"system[2]" -> 9,
"system[3]" -> 10,
"pbus" -> 0)), // TSI is on the pbus, so serial-tl and pbus should be on the same node
acdNoCParams = NoCParams(
topology = Mesh2D(4, 4),
channelParamGen = (a, b) => UserChannelParams(Seq.fill(3) { UserVirtualChannelParams(3) }, unifiedBuffer = false),
routerParams = (i) => UserRouterParams(combineRCVA=true, combineSAST=true),
routingRelation = NonblockingVirtualSubnetworksRouting(Mesh2DDimensionOrderedRouting(), 3, 1)),
beNoCParams = NoCParams(
topology = Mesh2D(4, 4),
channelParamGen = (a, b) => UserChannelParams(Seq.fill(2) { UserVirtualChannelParams(3) }, unifiedBuffer = false),
routerParams = (i) => UserRouterParams(combineRCVA=true, combineSAST=true),
routingRelation = NonblockingVirtualSubnetworksRouting(Mesh2DDimensionOrderedRouting(), 2, 1)),
beDivision = 4
)) ++
new freechips.rocketchip.subsystem.WithNBigCores(12) ++
new freechips.rocketchip.subsystem.WithNBanks(4) ++
new chipyard.config.WithSystemBusWidth(128) ++
new chipyard.config.AbstractConfig
)

3
generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala
View File

@@ -52,6 +52,9 @@ class MMIORocketConfig extends Config(
new chipyard.config.AbstractConfig)
class LBWIFRocketConfig extends Config(
new chipyard.config.WithOffchipBusFrequency(500) ++
new testchipip.WithOffchipBusClient(MBUS) ++
new testchipip.WithOffchipBus ++
new testchipip.WithSerialTLMem(isMainMemory=true) ++ // set lbwif memory base to DRAM_BASE, use as main memory
new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove AXI4 backing memory
new freechips.rocketchip.subsystem.WithNBigCores(1) ++

1
generators/chipyard/src/main/scala/config/RocketConfigs.scala
View File

@@ -69,7 +69,6 @@ class MulticlockRocketConfig extends Config(
new chipyard.config.WithFbusToSbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between FBUS and SBUS
new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS
new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS
new testchipip.WithAsynchronousSerialSlaveCrossing ++ // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS
new chipyard.config.AbstractConfig)
class CustomIOChipTopRocketConfig extends Config(

8
generators/chipyard/src/main/scala/config/TutorialConfigs.scala
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@@ -90,14 +90,14 @@ class TutorialNoCConfig extends Config(
// The inNodeMapping and outNodeMapping values are the physical identifiers of
// routers on the topology to map the agents to. Try changing these to any
// value within the range [0, topology.nNodes)
new constellation.soc.WithPbusNoC(constellation.protocol.TLNoCParams(
new constellation.soc.WithPbusNoC(constellation.protocol.GlobalTLNoCParams(
constellation.protocol.DiplomaticNetworkNodeMapping(
inNodeMapping = ListMap("Core" -> 7),
outNodeMapping = ListMap(
"pbus" -> 8, "uart" -> 9, "control" -> 10, "gcd" -> 11,
"writeQueue[0]" -> 0, "writeQueue[1]" -> 1, "tailChain[0]" -> 2))
), true) ++
new constellation.soc.WithSbusNoC(constellation.protocol.TLNoCParams(
)) ++
new constellation.soc.WithSbusNoC(constellation.protocol.GlobalTLNoCParams(
constellation.protocol.DiplomaticNetworkNodeMapping(
inNodeMapping = ListMap(
"Core 0" -> 0, "Core 1" -> 1,
@@ -105,7 +105,7 @@ class TutorialNoCConfig extends Config(
outNodeMapping = ListMap(
"system[0]" -> 3, "system[1]" -> 4, "system[2]" -> 5, "system[3]" -> 6,
"pbus" -> 7))
), true) ++
)) ++
new chipyard.example.WithGCD ++
new chipyard.harness.WithLoopbackNIC ++
new icenet.WithIceNIC ++

2
generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala
View File

@@ -15,6 +15,8 @@ import chipyard._
import chipyard.clocking._
import testchipip.{OffchipBusKey}
import testchipip.{OffchipBusKey}
// The default RocketChip BaseSubsystem drives its diplomatic clock graph
// with the implicit clocks of Subsystem. Don't do that, instead we extend
// the diplomacy graph upwards into the ChipTop, where we connect it to

8
generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala
View File

@@ -1,7 +1,7 @@
package chipyard.config
import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.subsystem.{SystemBusKey, BankedL2Key, CoherenceManagerWrapper, InclusiveCacheKey}
import freechips.rocketchip.subsystem._
import freechips.rocketchip.diplomacy.{DTSTimebase}
import sifive.blocks.inclusivecache.{InclusiveCachePortParameters}
@@ -10,6 +10,10 @@ class WithBroadcastManager extends Config((site, here, up) => {
case BankedL2Key => up(BankedL2Key, site).copy(coherenceManager = CoherenceManagerWrapper.broadcastManager)
})
class WithBroadcastParams(params: BroadcastParams) extends Config((site, here, up) => {
case BroadcastKey => params
})
class WithSystemBusWidth(bitWidth: Int) extends Config((site, here, up) => {
case SystemBusKey => up(SystemBusKey, site).copy(beatBytes=bitWidth/8)
})
@@ -26,4 +30,4 @@ class WithInclusiveCacheInteriorBuffer(buffer: InclusiveCachePortParameters = In
// Adds buffers on the exterior of the inclusive LLC, to improve PD
class WithInclusiveCacheExteriorBuffer(buffer: InclusiveCachePortParameters = InclusiveCachePortParameters.full) extends Config((site, here, up) => {
case InclusiveCacheKey => up(InclusiveCacheKey).copy(bufInnerExterior=buffer, bufOuterExterior=buffer)
})
})

4
generators/chipyard/src/main/scala/example/FlatChipTop.scala
View File

@@ -109,8 +109,8 @@ class FlatChipTop(implicit p: Parameters) extends LazyModule with HasChipyardPor
//=========================
// Serialized TileLink
//=========================
val (serial_tl_pad, serialTLIOCells) = IOCell.generateIOFromSignal(system.serial_tl.get.getWrappedValue, "serial_tl", p(IOCellKey))
ports = ports :+ SerialTLPort(() => serial_tl_pad, p(SerialTLKey).get, system.serdesser.get, 0)
val (serial_tl_pad, serialTLIOCells) = IOCell.generateIOFromSignal(system.serial_tls(0).getWrappedValue, "serial_tl", p(IOCellKey))
ports = ports :+ SerialTLPort(() => serial_tl_pad, p(SerialTLKey)(0), system.serdessers(0), 0)
//=========================
// JTAG/Debug

9
generators/chipyard/src/main/scala/example/FlatTestHarness.scala
View File

@@ -39,8 +39,8 @@ class FlatTestHarness(implicit val p: Parameters) extends Module {
dut.custom_boot_pad := PlusArg("custom_boot_pin", width=1)
// Serialized TL
val sVal = p(SerialTLKey).get
val serialTLManagerParams = sVal.serialTLManagerParams.get
val sVal = p(SerialTLKey)(0)
val serialTLManagerParams = sVal.manager.get
require(serialTLManagerParams.isMemoryDevice)
withClockAndReset(clock, reset) {
@@ -49,10 +49,11 @@ class FlatTestHarness(implicit val p: Parameters) extends Module {
dut.serial_tl_pad.clock := clock
}
val harnessRAM = TSIHarness.connectRAM(
lazyDut.system.serdesser.get,
p(SerialTLKey)(0),
lazyDut.system.serdessers(0),
serial_bits,
reset)
io.success := SimTSI.connect(Some(harnessRAM.module.io.tsi), clock, reset)
io.success := SimTSI.connect(harnessRAM.module.io.tsi, clock, reset)
}

4
generators/chipyard/src/main/scala/harness/HarnessBinders.scala
View File

@@ -215,13 +215,13 @@ class WithSimTSIOverSerialTL extends HarnessBinder({
if (DataMirror.directionOf(port.io.clock) == Direction.Input) {
port.io.clock := th.harnessBinderClock
}
val ram = LazyModule(new SerialRAM(port.serdesser)(port.serdesser.p))
val ram = LazyModule(new SerialRAM(port.serdesser, port.params)(port.serdesser.p))
Module(ram.module)
ram.module.io.ser <> port.io.bits
val tsi = Module(new SimTSI)
tsi.io.clock := th.harnessBinderClock
tsi.io.reset := th.harnessBinderReset
tsi.io.tsi <> ram.module.io.tsi
tsi.io.tsi <> ram.module.io.tsi.get
val exit = tsi.io.exit
val success = exit === 1.U
val error = exit >= 2.U

10
generators/chipyard/src/main/scala/iobinders/IOBinders.scala
View File

@@ -334,10 +334,10 @@ class WithDebugIOCells extends OverrideLazyIOBinder({
class WithSerialTLIOCells extends OverrideIOBinder({
(system: CanHavePeripheryTLSerial) => {
val (ports, cells) = system.serial_tl.zipWithIndex.map({ case (s, id) =>
val (ports, cells) = system.serial_tls.zipWithIndex.map({ case (s, id) =>
val sys = system.asInstanceOf[BaseSubsystem]
val (port, cells) = IOCell.generateIOFromSignal(s.getWrappedValue, "serial_tl", sys.p(IOCellKey), abstractResetAsAsync = true)
(SerialTLPort(() => port, sys.p(SerialTLKey).get, system.serdesser.get, id), cells)
val (port, cells) = IOCell.generateIOFromSignal(s.getWrappedValue, s"serial_tl_$id", sys.p(IOCellKey), abstractResetAsAsync = true)
(SerialTLPort(() => port, sys.p(SerialTLKey)(id), system.serdessers(id), id), cells)
}).unzip
(ports.toSeq, cells.flatten.toSeq)
}
@@ -345,11 +345,11 @@ class WithSerialTLIOCells extends OverrideIOBinder({
class WithSerialTLPunchthrough extends OverrideIOBinder({
(system: CanHavePeripheryTLSerial) => {
val (ports, cells) = system.serial_tl.zipWithIndex.map({ case (s, id) =>
val (ports, cells) = system.serial_tls.zipWithIndex.map({ case (s, id) =>
val sys = system.asInstanceOf[BaseSubsystem]
val port = IO(chiselTypeOf(s.getWrappedValue))
port <> s.getWrappedValue
(SerialTLPort(() => port, sys.p(SerialTLKey).get, system.serdesser.get, id), Nil)
(SerialTLPort(() => port, sys.p(SerialTLKey)(id), system.serdessers(id), id), Nil)
}).unzip
(ports.toSeq, cells.flatten.toSeq)
}

2
generators/constellation

Submodule generators/constellation updated: 03ed9e4ecd...3632183fd1

4
generators/firechip/src/main/scala/BridgeBinders.scala
View File

@@ -69,7 +69,7 @@ class WithTSIBridgeAndHarnessRAMOverSerialTL extends HarnessBinder({
case (th: FireSim, port: SerialTLPort) => {
val bits = port.io.bits
port.io.clock := th.harnessBinderClock
val ram = LazyModule(new SerialRAM(port.serdesser)(Parameters.empty))
val ram = LazyModule(new SerialRAM(port.serdesser, port.params)(port.serdesser.p))
Module(ram.module)
ram.module.io.ser <> port.io.bits
@@ -78,7 +78,7 @@ class WithTSIBridgeAndHarnessRAMOverSerialTL extends HarnessBinder({
// If FASED bridge is attached, loadmem widget is present
val hasMainMemory = th.chipParameters(th.p(MultiChipIdx))(ExtMem).isDefined
val mainMemoryName = Option.when(hasMainMemory)(MainMemoryConsts.globalName(th.p(MultiChipIdx)))
TSIBridge(th.harnessBinderClock, ram.module.io.tsi, mainMemoryName, th.harnessBinderReset.asBool)(th.p)
TSIBridge(th.harnessBinderClock, ram.module.io.tsi.get, mainMemoryName, th.harnessBinderReset.asBool)(th.p)
}
})

18
generators/firechip/src/main/scala/TargetConfigs.scala
View File

@@ -126,14 +126,14 @@ class WithFireSimHighPerfClocking extends Config(
new chipyard.config.WithPeripheryBusFrequency(3200.0) ++
new chipyard.config.WithSystemBusFrequency(3200.0) ++
new chipyard.config.WithFrontBusFrequency(3200.0) ++
new chipyard.config.WithControlBusFrequency(3200.0) ++
// Optional: These three configs put the DRAM memory system in it's own clock domain.
// Removing the first config will result in the FASED timing model running
// at the pbus freq (above, 3.2 GHz), which is outside the range of valid DDR3 speedgrades.
// 1 GHz matches the FASED default, using some other frequency will require
// runnings the FASED runtime configuration generator to generate faithful DDR3 timing values.
new chipyard.config.WithMemoryBusFrequency(1000.0) ++
new chipyard.config.WithAsynchrousMemoryBusCrossing ++
new testchipip.WithAsynchronousSerialSlaveCrossing
new chipyard.config.WithAsynchrousMemoryBusCrossing
)
// Tweaks that are generally applied to all firesim configs setting a single clock domain at 1000 MHz
@@ -142,8 +142,10 @@ class WithFireSimConfigTweaks extends Config(
// Using some other frequency will require runnings the FASED runtime configuration generator
// to generate faithful DDR3 timing values.
new chipyard.config.WithSystemBusFrequency(1000.0) ++
new chipyard.config.WithControlBusFrequency(1000.0) ++
new chipyard.config.WithPeripheryBusFrequency(1000.0) ++
new chipyard.config.WithMemoryBusFrequency(1000.0) ++
new chipyard.config.WithFrontBusFrequency(1000.0) ++
new WithFireSimDesignTweaks
)
@@ -189,13 +191,14 @@ class WithFireSimTestChipConfigTweaks extends Config(
new chipyard.config.WithSystemBusFrequency(500.0) ++ // Realistic system bus frequency
new chipyard.config.WithMemoryBusFrequency(1000.0) ++ // Needs to be 1000 MHz to model DDR performance accurately
new chipyard.config.WithPeripheryBusFrequency(500.0) ++ // Match the sbus and pbus frequency
new chipyard.config.WithFrontBusFrequency(500.0) ++ // Match the sbus and fbus frequency
new chipyard.config.WithControlBusFrequency(500.0) ++ // Match the sbus and cbus frequency
new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "pbus", "fbus", "cbus", "implicit"), Seq("tile"))) ++
// Crossing specifications
new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS
new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS
new freechips.rocketchip.subsystem.WithRationalRocketTiles ++ // Add rational crossings between RocketTile and uncore
new boom.common.WithRationalBoomTiles ++ // Add rational crossings between BoomTile and uncore
new testchipip.WithAsynchronousSerialSlaveCrossing ++ // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS
new WithFireSimDesignTweaks
)
@@ -250,10 +253,17 @@ class FireSimSmallSystemConfig extends Config(
new WithDefaultMemModel ++
new WithBootROM ++
new chipyard.config.WithPeripheryBusFrequency(3200.0) ++
new chipyard.config.WithControlBusFrequency(3200.0) ++
new chipyard.config.WithSystemBusFrequency(3200.0) ++
new chipyard.config.WithFrontBusFrequency(3200.0) ++
new chipyard.config.WithMemoryBusFrequency(3200.0) ++
new WithoutClockGating ++
new WithoutTLMonitors ++
new freechips.rocketchip.subsystem.WithExtMemSize(1 << 28) ++
new testchipip.WithDefaultSerialTL ++
new testchipip.WithSerialTL(Seq(testchipip.SerialTLParams(
client = Some(testchipip.SerialTLClientParams(idBits = 4)),
width = 32
))) ++
new testchipip.WithBlockDevice ++
new chipyard.config.WithUARTInitBaudRate(BigInt(3686400L)) ++
new freechips.rocketchip.subsystem.WithInclusiveCache(nWays = 2, capacityKB = 64) ++

2
generators/testchipip

Submodule generators/testchipip updated: c4c0774f5f...50a05b0782