wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

[ci skip] Add inline comments on some of the clocking fragments

Browse Source
This commit is contained in:
Jerry Zhao
2023-12-16 12:24:22 -08:00
committed by GitHub
parent b37b6b0d9b
commit 2e77867577
1 changed files with 4 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala
View File

@@ -111,18 +111,22 @@ class WithOffchipBusFrequency(freqMHz: Double) extends Config((site, here, up) =
class WithRationalMemoryBusCrossing extends WithSbusToMbusCrossingType(RationalCrossing(Symmetric))
class WithAsynchrousMemoryBusCrossing extends WithSbusToMbusCrossingType(AsynchronousCrossing())
// Remove the tile clock gaters in this system
class WithNoTileClockGaters extends Config((site, here, up) => {
case ChipyardPRCIControlKey => up(ChipyardPRCIControlKey).copy(enableTileClockGating = false)
})
// Remove the tile reset control blocks in this system
class WithNoTileResetSetters extends Config((site, here, up) => {
case ChipyardPRCIControlKey => up(ChipyardPRCIControlKey).copy(enableTileResetSetting = false)
})
// Remove the global reset synchronizers in this system
class WithNoResetSynchronizers extends Config((site, here, up) => {
case ChipyardPRCIControlKey => up(ChipyardPRCIControlKey).copy(enableResetSynchronizers = false)
})
// Remove any ClockTap ports in this system
class WithNoClockTap extends Config((site, here, up) => {
case ClockTapKey => None
})