diff --git a/.gitmodules b/.gitmodules index db0837ec..e1768873 100644 --- a/.gitmodules +++ b/.gitmodules @@ -142,3 +142,6 @@ [submodule "tools/install-circt"] path = tools/install-circt url = https://github.com/circt/install-circt/ +[submodule "toolchains/riscv-tools/riscv-spike-devices"] + path = toolchains/riscv-tools/riscv-spike-devices + url = https://github.com/ucb-bar/spike-devices.git diff --git a/common.mk b/common.mk index 5e0e2fcd..f525b526 100644 --- a/common.mk +++ b/common.mk @@ -28,7 +28,6 @@ EXTRA_SIM_CXXFLAGS ?= EXTRA_SIM_LDFLAGS ?= EXTRA_SIM_SOURCES ?= EXTRA_SIM_REQS ?= -ENABLE_CUSTOM_FIRRTL_PASS += $(ENABLE_YOSYS_FLOW) ifneq ($(ASPECTS), ) comma = , diff --git a/docs/Software/Spike.rst b/docs/Software/Spike.rst index e9abe0c0..10fa8429 100644 --- a/docs/Software/Spike.rst +++ b/docs/Software/Spike.rst @@ -50,3 +50,24 @@ Spike-as-a-Tile can be configured with custom IPC, commit logging, and other beh * ``+spike-fast-clint``: Enables fast-forwarding through WFI stalls by generating fake timer interrupts * ``+spike-debug``: Enables debug Spike logging * ``+spike-verbose``: Enables Spike commit-log generation + +Adding a new spike device model +------------------------------- + +Spike comes with a few functional device models such as UART, CLINT, and PLIC. +However, you may want to add custom device models into Spike such as a block device. +Example devices are in the ``toolchains/riscv-tools/riscv-spike-devices`` directory. +These devices are compiled as a shared library that can be dynamically linked to Spike. + +To compile these plugins, run ``make`` inside ``toolchains/riscv-tools/riscv-spike-devices``. This will generate a ``libspikedevices.so``. + +To hook up a block device to spike and provide a default image to initialize the block device, run + +.. code-block:: shell + + spike --extlib=libspikedevices.so --device="iceblk,img=" + +. + +The ``--device`` option consists of the device name and arguments. +In the above example ``iceblk`` is the device name and ``img=`` is the argument passed on to the plugin device. diff --git a/docs/VLSI/Sky130-Commercial-Tutorial.rst b/docs/VLSI/Sky130-Commercial-Tutorial.rst index 70be799e..92e4330c 100644 --- a/docs/VLSI/Sky130-Commercial-Tutorial.rst +++ b/docs/VLSI/Sky130-Commercial-Tutorial.rst @@ -123,8 +123,7 @@ The ``buildfile`` make target has dependencies on both (1) the Verilog that is e and (2) the mapping of memory instances in the design to SRAM macros; all files related to these two steps reside in the ``generated-src/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop`` directory. Note that the files in ``generated-src`` vary for each tool/technology flow. -This especially applies to the Sky130 Commercial vs OpenROAD tutorial flows -(due to the ``ENABLE_YOSYS_FLOW`` flag present for the OpenROAD flow), so these flows should be run in separate +This especially applies to the Sky130 Commercial vs OpenROAD tutorial flows, so these flows should be run in separate chipyard installations. If the wrong sources are generated, simply run ``make buildfile -B`` to rebuild all targets correctly. diff --git a/docs/VLSI/Sky130-OpenROAD-Tutorial.rst b/docs/VLSI/Sky130-OpenROAD-Tutorial.rst index f9bbbffb..0c138d66 100644 --- a/docs/VLSI/Sky130-OpenROAD-Tutorial.rst +++ b/docs/VLSI/Sky130-OpenROAD-Tutorial.rst @@ -49,7 +49,7 @@ Prerequisites * OpenROAD flow tools (NOTE: tutorial may break with different tool versions): * **Yosys 0.27+3** (synthesis), install `using conda `__ or `from source `__ - * **OpenROAD v2.0-7070-g0264023b6** (place-and-route), install `using conda `__ (note that GUI is disabled in conda package) or + * **OpenROAD v2.0-7070-g0264023b6** (place-and-route), install `using conda `__ (note that GUI is disabled in conda package) or `from source `__ (git hash: 0264023b6c2a8ae803b8d440478d657387277d93) * **KLayout 0.28.5** (DEF to GDSII conversion, DRC), install `using conda `__ or `from source `__ * **Magic 8.3.376** (DRC), install `using conda `__ or `from source `__ @@ -161,8 +161,7 @@ The ``buildfile`` make target has dependencies on both (1) the Verilog that is e and (2) the mapping of memory instances in the design to SRAM macros; all files related to these two steps reside in the ``generated-src/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop`` directory. Note that the files in ``generated-src`` vary for each tool/technology flow. -This especially applies to the Sky130 Commercial vs OpenROAD tutorial flows -(due to the ``ENABLE_YOSYS_FLOW`` flag, explained below), so these flows should be run in separate +This especially applies to the Sky130 Commercial vs OpenROAD tutorial flows, so these flows should be run in separate chipyard installations. If the wrong sources are generated, simply run ``make buildfile -B`` to rebuild all targets correctly. @@ -175,7 +174,6 @@ which will cause additional variables to be set in ``tutorial.mk``, a few of whi * ``DESIGN_CONF`` and ``EXTRA_CONFS`` allow for additonal design-specific overrides of the Hammer IR in ``example-sky130.yml`` * ``VLSI_OBJ_DIR=build-sky130-openroad`` gives the build directory a unique name to allow running multiple flows in the same repo. Note that for the rest of the tutorial we will still refer to this directory in file paths as ``build``, again for brevity. * ``VLSI_TOP`` is by default ``ChipTop``, which is the name of the top-level Verilog module generated in the Chipyard SoC configs. By instead setting ``VLSI_TOP=Rocket``, we can use the Rocket core as the top-level module for the VLSI flow, which consists only of a single RISC-V core (and no caches, peripherals, buses, etc). This is useful to run through this tutorial quickly, and does not rely on any SRAMs. -* ``ENABLE_YOSYS_FLOW = 1`` is required for synthesis through Yosys. This reverts to the Scala FIRRTL Compiler so that unsupported multidimensional arrays are not generated in the Verilog. Running the VLSI Flow --------------------- @@ -275,7 +273,7 @@ This is because Magic and Netgen, as of the writing of this tutorial, do not hav so to view the DRC/LVS results for debugging you must launch the tool interactively, then run DRC/LVS checks, which is done by the ``generated-scripts/view_[drc|lvs]`` scripts. This is not the case for KLayout, which does have a loadable database format. -Below is the window you should see when loading the KLayout DRC results interactively. Note that most of these DRC errors are +Below is the window you should see when loading the KLayout DRC results interactively. Note that most of these DRC errors are from special rules relating to Sky130 SRAMs, which have been verified separately. In the future the KLayout tool plugin should blackbox these SRAM macros by default, but this feature does not exist yet. diff --git a/fpga/src/main/scala/arty/Configs.scala b/fpga/src/main/scala/arty/Configs.scala index 3e208060..1bf2b643 100644 --- a/fpga/src/main/scala/arty/Configs.scala +++ b/fpga/src/main/scala/arty/Configs.scala @@ -27,6 +27,8 @@ class WithArtyTweaks extends Config( new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++ new chipyard.config.WithDTSTimebase(32000) ++ new chipyard.config.WithSystemBusFrequency(32) ++ + new chipyard.config.WithFrontBusFrequency(32) ++ + new chipyard.config.WithControlBusFrequency(32) ++ new chipyard.config.WithPeripheryBusFrequency(32) ++ new testchipip.WithNoSerialTL ) diff --git a/fpga/src/main/scala/nexysvideo/Configs.scala b/fpga/src/main/scala/nexysvideo/Configs.scala index f31e38d1..01b095fa 100644 --- a/fpga/src/main/scala/nexysvideo/Configs.scala +++ b/fpga/src/main/scala/nexysvideo/Configs.scala @@ -33,6 +33,7 @@ class WithNexysVideoTweaks extends Config( new chipyard.config.WithFrontBusFrequency(50.0) ++ new chipyard.config.WithSystemBusFrequency(50.0) ++ new chipyard.config.WithPeripheryBusFrequency(50.0) ++ + new chipyard.config.WithControlBusFrequency(50.0) ++ new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++ new chipyard.clocking.WithPassthroughClockGenerator ++ new chipyard.config.WithNoDebug ++ // no jtag @@ -69,4 +70,4 @@ class TinyRocketNexysVideoConfig extends Config( new WithTinyNexysVideoTweaks ++ new chipyard.config.WithBroadcastManager ++ // no l2 new chipyard.TinyRocketConfig) - // DOC include end: WithTinyNexysVideoTweaks and Rocket \ No newline at end of file + // DOC include end: WithTinyNexysVideoTweaks and Rocket diff --git a/fpga/src/main/scala/vc707/Configs.scala b/fpga/src/main/scala/vc707/Configs.scala index b37064ac..124920d7 100644 --- a/fpga/src/main/scala/vc707/Configs.scala +++ b/fpga/src/main/scala/vc707/Configs.scala @@ -35,7 +35,7 @@ class WithSystemModifications extends Config((site, here, up) => { p.copy(hang = 0x10000, contentFileName = s"./fpga/src/main/resources/vc707/sdboot/build/sdboot.bin") } case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(size = site(VC7074GDDRSize)))) // set extmem to DDR size (note the size) - case SerialTLKey => None // remove serialized tl port + case SerialTLKey => Nil // remove serialized tl port }) class WithVC707Tweaks extends Config ( @@ -45,6 +45,8 @@ class WithVC707Tweaks extends Config ( new chipyard.config.WithMemoryBusFrequency(50.0) ++ new chipyard.config.WithSystemBusFrequency(50.0) ++ new chipyard.config.WithPeripheryBusFrequency(50.0) ++ + new chipyard.config.WithControlBusFrequency(50.0) ++ + new chipyard.config.WithFrontBusFrequency(50.0) ++ new chipyard.harness.WithHarnessBinderClockFreqMHz(50) ++ new WithFPGAFrequency(50) ++ // default 50MHz freq @@ -74,8 +76,11 @@ class BoomVC707Config extends Config ( ) class WithFPGAFrequency(fMHz: Double) extends Config ( - new chipyard.config.WithPeripheryBusFrequency(fMHz) ++ // assumes using PBUS as default freq. - new chipyard.config.WithMemoryBusFrequency(fMHz) + new chipyard.config.WithPeripheryBusFrequency(fMHz) ++ + new chipyard.config.WithMemoryBusFrequency(fMHz) ++ + new chipyard.config.WithSystemBusFrequency(fMHz) ++ + new chipyard.config.WithControlBusFrequency(fMHz) ++ + new chipyard.config.WithFrontBusFrequency(fMHz) ) class WithFPGAFreq25MHz extends WithFPGAFrequency(25) diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala index 35632961..32dc3c2c 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -36,7 +36,7 @@ class WithSystemModifications extends Config((site, here, up) => { p.copy(hang = 0x10000, contentFileName = s"./fpga/src/main/resources/vcu118/sdboot/build/sdboot.bin") } case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(size = site(VCU118DDRSize)))) // set extmem to DDR size - case SerialTLKey => None // remove serialized tl port + case SerialTLKey => Nil // remove serialized tl port }) // DOC include start: AbstractVCU118 and Rocket @@ -46,6 +46,7 @@ class WithVCU118Tweaks extends Config( new chipyard.clocking.WithPassthroughClockGenerator ++ new chipyard.config.WithMemoryBusFrequency(100) ++ new chipyard.config.WithSystemBusFrequency(100) ++ + new chipyard.config.WithControlBusFrequency(100) ++ new chipyard.config.WithPeripheryBusFrequency(100) ++ new WithFPGAFrequency(100) ++ // default 100MHz freq // harness binders @@ -76,7 +77,9 @@ class BoomVCU118Config extends Config( class WithFPGAFrequency(fMHz: Double) extends Config( new chipyard.harness.WithHarnessBinderClockFreqMHz(fMHz) ++ new chipyard.config.WithSystemBusFrequency(fMHz) ++ - new chipyard.config.WithPeripheryBusFrequency(fMHz) ++ // assumes using PBUS as default freq. + new chipyard.config.WithPeripheryBusFrequency(fMHz) ++ + new chipyard.config.WithControlBusFrequency(fMHz) ++ + new chipyard.config.WithFrontBusFrequency(fMHz) ++ new chipyard.config.WithMemoryBusFrequency(fMHz) ) diff --git a/generators/chipyard/src/main/resources/csrc/spiketile.cc b/generators/chipyard/src/main/resources/csrc/spiketile.cc index 3b14079b..5483cf6b 100644 --- a/generators/chipyard/src/main/resources/csrc/spiketile.cc +++ b/generators/chipyard/src/main/resources/csrc/spiketile.cc @@ -447,18 +447,6 @@ chipyard_simif_t::chipyard_simif_t(size_t icache_ways, use_stq(false), htif(nullptr), fast_clint(false), - cfg(std::make_pair(0, 0), - nullptr, - isastr, - "MSU", - "vlen:128,elen:64", - false, - endianness_little, - pmpregions, - std::vector(), - std::vector(), - false, - 0), accessed_tofrom_host(false), icache_ways(icache_ways), icache_sets(icache_sets), @@ -470,6 +458,19 @@ chipyard_simif_t::chipyard_simif_t(size_t icache_ways, mmio_inflight(false) { + cfg.initrd_bounds = std::make_pair(0, 0); + cfg.bootargs = nullptr; + cfg.isa = isastr; + cfg.priv = "MSU"; + cfg.varch = "vlen:128,elen:64"; + cfg.misaligned = false; + cfg.endianness = endianness_little; + cfg.pmpregions = pmpregions; + cfg.mem_layout = std::vector(); + cfg.hartids = std::vector(); + cfg.explicit_hartids = false; + cfg.trigger_count = 0; + icache.resize(icache_ways); for (auto &w : icache) { w.resize(icache_sets); diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala index d25d4fa3..a3ba679e 100644 --- a/generators/chipyard/src/main/scala/Subsystem.scala +++ b/generators/chipyard/src/main/scala/Subsystem.scala @@ -29,7 +29,7 @@ import testchipip.{CanHavePeripheryTLSerial, SerialTLKey} trait CanHaveHTIF { this: BaseSubsystem => // Advertise HTIF if system can communicate with fesvr if (this match { - case _: CanHavePeripheryTLSerial if p(SerialTLKey).nonEmpty => true + case _: CanHavePeripheryTLSerial if (p(SerialTLKey).size != 0) => true case _: HasPeripheryDebug if (!p(DebugModuleKey).isEmpty && p(ExportDebug).dmi) => true case _ => false }) { diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index 43cfc110..96794546 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -54,15 +54,20 @@ class AbstractConfig extends Config( new chipyard.clocking.WithClockTapIOCells ++ // Default generate a clock tapio new chipyard.clocking.WithPassthroughClockGenerator ++ // Default punch out IOs to the Harness new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", // Default merge all the bus clocks - Seq("sbus", "mbus", "pbus", "fbus", "cbus", "implicit"), Seq("tile"))) ++ + Seq("sbus", "mbus", "pbus", "fbus", "cbus", "obus", "implicit"), Seq("tile"))) ++ new chipyard.config.WithPeripheryBusFrequency(500.0) ++ // Default 500 MHz pbus new chipyard.config.WithMemoryBusFrequency(500.0) ++ // Default 500 MHz mbus + new chipyard.config.WithControlBusFrequency(500.0) ++ // Default 500 MHz cbus + new chipyard.config.WithSystemBusFrequency(500.0) ++ // Default 500 MHz sbus + new chipyard.config.WithFrontBusFrequency(500.0) ++ // Default 500 MHz fbus + new chipyard.config.WithOffchipBusFrequency(500.0) ++ // Default 500 MHz obus new testchipip.WithCustomBootPin ++ // add a custom-boot-pin to support pin-driven boot address new testchipip.WithBootAddrReg ++ // add a boot-addr-reg for configurable boot address - new testchipip.WithSerialTLClientIdBits(4) ++ // support up to 1 << 4 simultaneous requests from serialTL port - new testchipip.WithSerialTLWidth(32) ++ // fatten the serialTL interface to improve testing performance - new testchipip.WithDefaultSerialTL ++ // use serialized tilelink port to external serialadapter/harnessRAM + new testchipip.WithSerialTL(Seq(testchipip.SerialTLParams( // add a serial-tilelink interface + client = Some(testchipip.SerialTLClientParams(idBits = 4)), // serial-tilelink interface will master the FBUS, and support 4 idBits + width = 32 // serial-tilelink interface with 32 lanes + ))) ++ new chipyard.config.WithDebugModuleAbstractDataWords(8) ++ // increase debug module data capacity new chipyard.config.WithBootROM ++ // use default bootrom new chipyard.config.WithUART ++ // add a UART diff --git a/generators/chipyard/src/main/scala/config/ChipConfigs.scala b/generators/chipyard/src/main/scala/config/ChipConfigs.scala index c9ff068d..e3d18375 100644 --- a/generators/chipyard/src/main/scala/config/ChipConfigs.scala +++ b/generators/chipyard/src/main/scala/config/ChipConfigs.scala @@ -23,8 +23,8 @@ class ChipLikeRocketConfig extends Config( // Set up I/O //================================== new testchipip.WithSerialTLWidth(4) ++ // 4bit wide Serialized TL interface to minimize IO - new testchipip.WithSerialTLBackingMemory ++ // Configure the off-chip memory accessible over serial-tl as backing memory - new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 4L) ++ // 4GB max external memory + new testchipip.WithSerialTLMem(size = (1 << 30) * 4L) ++ // Configure the off-chip memory accessible over serial-tl as backing memory + new freechips.rocketchip.subsystem.WithNoMemPort ++ // Remove axi4 mem port new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ // 1 memory channel //================================== @@ -89,6 +89,9 @@ class ChipBringupHostConfig extends Config( new chipyard.config.WithFrontBusFrequency(75.0) ++ // run all buses of this system at 75 MHz new chipyard.config.WithMemoryBusFrequency(75.0) ++ new chipyard.config.WithPeripheryBusFrequency(75.0) ++ + new chipyard.config.WithSystemBusFrequency(75.0) ++ + new chipyard.config.WithControlBusFrequency(75.0) ++ + new chipyard.config.WithOffchipBusFrequency(75.0) ++ // Base is the no-cores config new chipyard.NoCoresConfig) diff --git a/generators/chipyard/src/main/scala/config/NoCConfigs.scala b/generators/chipyard/src/main/scala/config/NoCConfigs.scala index 0b6be558..66cb1aa2 100644 --- a/generators/chipyard/src/main/scala/config/NoCConfigs.scala +++ b/generators/chipyard/src/main/scala/config/NoCConfigs.scala @@ -6,6 +6,7 @@ import freechips.rocketchip.subsystem.{SBUS, MBUS} import constellation.channel._ import constellation.routing._ +import constellation.router._ import constellation.topology._ import constellation.noc._ import constellation.soc.{GlobalNoCParams} @@ -45,7 +46,7 @@ import scala.collection.immutable.ListMap * | SI:Core 2 | SO:system[0] | SO:system[1] | SI:Core 3 | * |(0)___________|(1)___________|(2)___________|(3)___________| * | FBus | Core 0 | Core 1 | Pbus | - * | SI:serial-tl | SI:Core 0 | SI:Core 1 | SO:pbus | + * | SI:serial_tl | SI:Core 0 | SI:Core 1 | SO:pbus | * |______________|______________|______________|______________| * * |(0)___________|(1)___________|(2)___________|(3)___________| @@ -62,37 +63,37 @@ import scala.collection.immutable.ListMap */ // DOC include start: MultiNoCConfig class MultiNoCConfig extends Config( - new constellation.soc.WithCbusNoC(constellation.protocol.TLNoCParams( + new constellation.soc.WithCbusNoC(constellation.protocol.SimpleTLNoCParams( constellation.protocol.DiplomaticNetworkNodeMapping( inNodeMapping = ListMap( - "serial-tl" -> 0), + "serial_tl" -> 0), outNodeMapping = ListMap( - "error" -> 1, "l2[0]" -> 2, "pbus" -> 3, "plic" -> 4, + "error" -> 1, "ctrls[0]" -> 2, "pbus" -> 3, "plic" -> 4, "clint" -> 5, "dmInner" -> 6, "bootrom" -> 7, "clock" -> 8)), NoCParams( topology = TerminalRouter(BidirectionalLine(9)), channelParamGen = (a, b) => UserChannelParams(Seq.fill(5) { UserVirtualChannelParams(4) }), routingRelation = NonblockingVirtualSubnetworksRouting(TerminalRouterRouting(BidirectionalLineRouting()), 5, 1)) )) ++ - new constellation.soc.WithMbusNoC(constellation.protocol.TLNoCParams( + new constellation.soc.WithMbusNoC(constellation.protocol.SimpleTLNoCParams( constellation.protocol.DiplomaticNetworkNodeMapping( inNodeMapping = ListMap( "L2 InclusiveCache[0]" -> 1, "L2 InclusiveCache[1]" -> 2, "L2 InclusiveCache[2]" -> 5, "L2 InclusiveCache[3]" -> 6), outNodeMapping = ListMap( "system[0]" -> 0, "system[1]" -> 3, "system[2]" -> 4 , "system[3]" -> 7, - "serdesser" -> 0)), + "serial_tl_0" -> 0)), NoCParams( topology = TerminalRouter(BidirectionalTorus1D(8)), channelParamGen = (a, b) => UserChannelParams(Seq.fill(10) { UserVirtualChannelParams(4) }), routingRelation = BlockingVirtualSubnetworksRouting(TerminalRouterRouting(BidirectionalTorus1DShortestRouting()), 5, 2)) )) ++ - new constellation.soc.WithSbusNoC(constellation.protocol.TLNoCParams( + new constellation.soc.WithSbusNoC(constellation.protocol.SimpleTLNoCParams( constellation.protocol.DiplomaticNetworkNodeMapping( inNodeMapping = ListMap( "Core 0" -> 1, "Core 1" -> 2, "Core 2" -> 4 , "Core 3" -> 7, "Core 4" -> 8, "Core 5" -> 11, "Core 6" -> 13, "Core 7" -> 14, - "serial-tl" -> 0), + "serial_tl" -> 0), outNodeMapping = ListMap( "system[0]" -> 5, "system[1]" -> 6, "system[2]" -> 9, "system[3]" -> 10, "pbus" -> 3)), @@ -133,7 +134,7 @@ class MultiNoCConfig extends Config( * Core 6 | SI | Core 6 | 16 * Core 7 | SI | Core 7 | 18 * Core 8 | SI | Core 8 | 19 - * fbus | SI | serial-tl | 9 + * fbus | SI | serial_tl | 9 * pbus | SO | pbus | 4 * L2 0 | SO | system[0] | 0 * L2 1 | SO | system[1] | 2 @@ -145,7 +146,7 @@ class MultiNoCConfig extends Config( * L2 3 | MI | Cache[3] | 6 * DRAM 0 | MO | system[0] | 3 * DRAM 1 | MO | system[1] | 5 - * extram | MO | serdesser | 9 + * extram | MO | serial_tl_0 | 9 */ // DOC include start: SharedNoCConfig class SharedNoCConfig extends Config( @@ -162,24 +163,24 @@ class SharedNoCConfig extends Config( BidirectionalLineRouting()))), 10, 2) ) )) ++ - new constellation.soc.WithMbusNoC(constellation.protocol.TLNoCParams( + new constellation.soc.WithMbusNoC(constellation.protocol.GlobalTLNoCParams( constellation.protocol.DiplomaticNetworkNodeMapping( inNodeMapping = ListMap( "Cache[0]" -> 0, "Cache[1]" -> 2, "Cache[2]" -> 8, "Cache[3]" -> 6), outNodeMapping = ListMap( "system[0]" -> 3, "system[1]" -> 5, - "serdesser" -> 9)) - ), true) ++ - new constellation.soc.WithSbusNoC(constellation.protocol.TLNoCParams( + "serial_tl_0" -> 9)) + )) ++ + new constellation.soc.WithSbusNoC(constellation.protocol.GlobalTLNoCParams( constellation.protocol.DiplomaticNetworkNodeMapping( inNodeMapping = ListMap( - "serial-tl" -> 9, "Core 0" -> 2, + "serial_tl" -> 9, "Core 0" -> 2, "Core 1" -> 10, "Core 2" -> 11, "Core 3" -> 13, "Core 4" -> 14, "Core 5" -> 15, "Core 6" -> 16, "Core 7" -> 18, "Core 8" -> 19), outNodeMapping = ListMap( "system[0]" -> 0, "system[1]" -> 2, "system[2]" -> 8, "system[3]" -> 6, "pbus" -> 4)) - ), true) ++ + )) ++ new freechips.rocketchip.subsystem.WithNBigCores(8) ++ new freechips.rocketchip.subsystem.WithNBanks(4) ++ new freechips.rocketchip.subsystem.WithNMemoryChannels(2) ++ @@ -187,8 +188,9 @@ class SharedNoCConfig extends Config( ) // DOC include end: SharedNoCConfig +// This Config implements a simple ring interconnect for the system bus class SbusRingNoCConfig extends Config( - new constellation.soc.WithSbusNoC(constellation.protocol.TLNoCParams( + new constellation.soc.WithSbusNoC(constellation.protocol.SplitACDxBETLNoCParams( constellation.protocol.DiplomaticNetworkNodeMapping( inNodeMapping = ListMap( "Core 0" -> 0, @@ -199,19 +201,67 @@ class SbusRingNoCConfig extends Config( "Core 5" -> 5, "Core 6" -> 6, "Core 7" -> 7, - "serial-tl" -> 8), + "serial_tl" -> 8), outNodeMapping = ListMap( "system[0]" -> 9, "system[1]" -> 10, "system[2]" -> 11, "system[3]" -> 12, "pbus" -> 8)), // TSI is on the pbus, so serial-tl and pbus should be on the same node - NoCParams( + acdNoCParams = NoCParams( topology = UnidirectionalTorus1D(13), - channelParamGen = (a, b) => UserChannelParams(Seq.fill(10) { UserVirtualChannelParams(4) }), - routingRelation = NonblockingVirtualSubnetworksRouting(UnidirectionalTorus1DDatelineRouting(), 5, 2)) + channelParamGen = (a, b) => UserChannelParams(Seq.fill(6) { UserVirtualChannelParams(4) }), + routingRelation = NonblockingVirtualSubnetworksRouting(UnidirectionalTorus1DDatelineRouting(), 3, 2)), + beNoCParams = NoCParams( + topology = UnidirectionalTorus1D(13), + channelParamGen = (a, b) => UserChannelParams(Seq.fill(4) { UserVirtualChannelParams(1) }), + routingRelation = NonblockingVirtualSubnetworksRouting(UnidirectionalTorus1DDatelineRouting(), 2, 2)) )) ++ new freechips.rocketchip.subsystem.WithNBigCores(8) ++ new freechips.rocketchip.subsystem.WithNBanks(4) ++ new chipyard.config.AbstractConfig ) + +// This config integrates a mesh interconnect for the system bus, and divides the system bus +// tilelink messages across two isolated interconnects +class SbusMeshNoCConfig extends Config( + new constellation.soc.WithSbusNoC(constellation.protocol.SplitACDxBETLNoCParams( + constellation.protocol.DiplomaticNetworkNodeMapping( + inNodeMapping = ListMap( + "Core 0 " -> 0, + "Core 1 " -> 1, + "Core 2 " -> 2, + "Core 3 " -> 3, + "Core 4 " -> 4, + "Core 5 " -> 7, + "Core 6 " -> 8, + "Core 7 " -> 11, + "Core 8 " -> 12, + "Core 9 " -> 13, + "Core 10 " -> 14, + "Core 11 " -> 15, + "serial-tl" -> 0), + outNodeMapping = ListMap( + "system[0]" -> 5, + "system[1]" -> 6, + "system[2]" -> 9, + "system[3]" -> 10, + "pbus" -> 0)), // TSI is on the pbus, so serial-tl and pbus should be on the same node + acdNoCParams = NoCParams( + topology = Mesh2D(4, 4), + channelParamGen = (a, b) => UserChannelParams(Seq.fill(3) { UserVirtualChannelParams(3) }, unifiedBuffer = false), + routerParams = (i) => UserRouterParams(combineRCVA=true, combineSAST=true), + routingRelation = NonblockingVirtualSubnetworksRouting(Mesh2DDimensionOrderedRouting(), 3, 1)), + beNoCParams = NoCParams( + topology = Mesh2D(4, 4), + channelParamGen = (a, b) => UserChannelParams(Seq.fill(2) { UserVirtualChannelParams(3) }, unifiedBuffer = false), + routerParams = (i) => UserRouterParams(combineRCVA=true, combineSAST=true), + routingRelation = NonblockingVirtualSubnetworksRouting(Mesh2DDimensionOrderedRouting(), 2, 1)), + beDivision = 4 + )) ++ + new freechips.rocketchip.subsystem.WithNBigCores(12) ++ + new freechips.rocketchip.subsystem.WithNBanks(4) ++ + new chipyard.config.WithSystemBusWidth(128) ++ + new chipyard.config.AbstractConfig +) + diff --git a/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala b/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala index a712e434..5473b99e 100644 --- a/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala +++ b/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala @@ -52,6 +52,9 @@ class MMIORocketConfig extends Config( new chipyard.config.AbstractConfig) class LBWIFRocketConfig extends Config( + new chipyard.config.WithOffchipBusFrequency(500) ++ + new testchipip.WithOffchipBusClient(MBUS) ++ + new testchipip.WithOffchipBus ++ new testchipip.WithSerialTLMem(isMainMemory=true) ++ // set lbwif memory base to DRAM_BASE, use as main memory new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove AXI4 backing memory new freechips.rocketchip.subsystem.WithNBigCores(1) ++ diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 740eafb9..929e8c59 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -69,7 +69,6 @@ class MulticlockRocketConfig extends Config( new chipyard.config.WithFbusToSbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between FBUS and SBUS new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS - new testchipip.WithAsynchronousSerialSlaveCrossing ++ // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS new chipyard.config.AbstractConfig) class CustomIOChipTopRocketConfig extends Config( diff --git a/generators/chipyard/src/main/scala/config/TutorialConfigs.scala b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala index edd9c438..cf93d0e4 100644 --- a/generators/chipyard/src/main/scala/config/TutorialConfigs.scala +++ b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala @@ -90,14 +90,14 @@ class TutorialNoCConfig extends Config( // The inNodeMapping and outNodeMapping values are the physical identifiers of // routers on the topology to map the agents to. Try changing these to any // value within the range [0, topology.nNodes) - new constellation.soc.WithPbusNoC(constellation.protocol.TLNoCParams( + new constellation.soc.WithPbusNoC(constellation.protocol.GlobalTLNoCParams( constellation.protocol.DiplomaticNetworkNodeMapping( inNodeMapping = ListMap("Core" -> 7), outNodeMapping = ListMap( "pbus" -> 8, "uart" -> 9, "control" -> 10, "gcd" -> 11, "writeQueue[0]" -> 0, "writeQueue[1]" -> 1, "tailChain[0]" -> 2)) - ), true) ++ - new constellation.soc.WithSbusNoC(constellation.protocol.TLNoCParams( + )) ++ + new constellation.soc.WithSbusNoC(constellation.protocol.GlobalTLNoCParams( constellation.protocol.DiplomaticNetworkNodeMapping( inNodeMapping = ListMap( "Core 0" -> 0, "Core 1" -> 1, @@ -105,7 +105,7 @@ class TutorialNoCConfig extends Config( outNodeMapping = ListMap( "system[0]" -> 3, "system[1]" -> 4, "system[2]" -> 5, "system[3]" -> 6, "pbus" -> 7)) - ), true) ++ + )) ++ new chipyard.example.WithGCD ++ new chipyard.harness.WithLoopbackNIC ++ new icenet.WithIceNIC ++ diff --git a/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala b/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala index eddcb803..8b061e5c 100644 --- a/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala @@ -15,6 +15,8 @@ import chipyard._ import chipyard.clocking._ import testchipip.{OffchipBusKey} +import testchipip.{OffchipBusKey} + // The default RocketChip BaseSubsystem drives its diplomatic clock graph // with the implicit clocks of Subsystem. Don't do that, instead we extend // the diplomacy graph upwards into the ChipTop, where we connect it to diff --git a/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala b/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala index b57ea4cb..7a45d293 100644 --- a/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala @@ -1,7 +1,7 @@ package chipyard.config import org.chipsalliance.cde.config.{Config} -import freechips.rocketchip.subsystem.{SystemBusKey, BankedL2Key, CoherenceManagerWrapper, InclusiveCacheKey} +import freechips.rocketchip.subsystem._ import freechips.rocketchip.diplomacy.{DTSTimebase} import sifive.blocks.inclusivecache.{InclusiveCachePortParameters} @@ -10,6 +10,10 @@ class WithBroadcastManager extends Config((site, here, up) => { case BankedL2Key => up(BankedL2Key, site).copy(coherenceManager = CoherenceManagerWrapper.broadcastManager) }) +class WithBroadcastParams(params: BroadcastParams) extends Config((site, here, up) => { + case BroadcastKey => params +}) + class WithSystemBusWidth(bitWidth: Int) extends Config((site, here, up) => { case SystemBusKey => up(SystemBusKey, site).copy(beatBytes=bitWidth/8) }) @@ -26,4 +30,4 @@ class WithInclusiveCacheInteriorBuffer(buffer: InclusiveCachePortParameters = In // Adds buffers on the exterior of the inclusive LLC, to improve PD class WithInclusiveCacheExteriorBuffer(buffer: InclusiveCachePortParameters = InclusiveCachePortParameters.full) extends Config((site, here, up) => { case InclusiveCacheKey => up(InclusiveCacheKey).copy(bufInnerExterior=buffer, bufOuterExterior=buffer) -}) +}) diff --git a/generators/chipyard/src/main/scala/example/FlatChipTop.scala b/generators/chipyard/src/main/scala/example/FlatChipTop.scala index b51a66cd..24fcad8e 100644 --- a/generators/chipyard/src/main/scala/example/FlatChipTop.scala +++ b/generators/chipyard/src/main/scala/example/FlatChipTop.scala @@ -109,8 +109,8 @@ class FlatChipTop(implicit p: Parameters) extends LazyModule with HasChipyardPor //========================= // Serialized TileLink //========================= - val (serial_tl_pad, serialTLIOCells) = IOCell.generateIOFromSignal(system.serial_tl.get.getWrappedValue, "serial_tl", p(IOCellKey)) - ports = ports :+ SerialTLPort(() => serial_tl_pad, p(SerialTLKey).get, system.serdesser.get, 0) + val (serial_tl_pad, serialTLIOCells) = IOCell.generateIOFromSignal(system.serial_tls(0).getWrappedValue, "serial_tl", p(IOCellKey)) + ports = ports :+ SerialTLPort(() => serial_tl_pad, p(SerialTLKey)(0), system.serdessers(0), 0) //========================= // JTAG/Debug diff --git a/generators/chipyard/src/main/scala/example/FlatTestHarness.scala b/generators/chipyard/src/main/scala/example/FlatTestHarness.scala index 5b3168b3..5f6c69f1 100644 --- a/generators/chipyard/src/main/scala/example/FlatTestHarness.scala +++ b/generators/chipyard/src/main/scala/example/FlatTestHarness.scala @@ -39,8 +39,8 @@ class FlatTestHarness(implicit val p: Parameters) extends Module { dut.custom_boot_pad := PlusArg("custom_boot_pin", width=1) // Serialized TL - val sVal = p(SerialTLKey).get - val serialTLManagerParams = sVal.serialTLManagerParams.get + val sVal = p(SerialTLKey)(0) + val serialTLManagerParams = sVal.manager.get require(serialTLManagerParams.isMemoryDevice) withClockAndReset(clock, reset) { @@ -49,10 +49,11 @@ class FlatTestHarness(implicit val p: Parameters) extends Module { dut.serial_tl_pad.clock := clock } val harnessRAM = TSIHarness.connectRAM( - lazyDut.system.serdesser.get, + p(SerialTLKey)(0), + lazyDut.system.serdessers(0), serial_bits, reset) - io.success := SimTSI.connect(Some(harnessRAM.module.io.tsi), clock, reset) + io.success := SimTSI.connect(harnessRAM.module.io.tsi, clock, reset) } diff --git a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala index 8530bb33..94321506 100644 --- a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala @@ -215,13 +215,13 @@ class WithSimTSIOverSerialTL extends HarnessBinder({ if (DataMirror.directionOf(port.io.clock) == Direction.Input) { port.io.clock := th.harnessBinderClock } - val ram = LazyModule(new SerialRAM(port.serdesser)(port.serdesser.p)) + val ram = LazyModule(new SerialRAM(port.serdesser, port.params)(port.serdesser.p)) Module(ram.module) ram.module.io.ser <> port.io.bits val tsi = Module(new SimTSI) tsi.io.clock := th.harnessBinderClock tsi.io.reset := th.harnessBinderReset - tsi.io.tsi <> ram.module.io.tsi + tsi.io.tsi <> ram.module.io.tsi.get val exit = tsi.io.exit val success = exit === 1.U val error = exit >= 2.U diff --git a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala index 7401452f..7894ba51 100644 --- a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala +++ b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala @@ -334,10 +334,10 @@ class WithDebugIOCells extends OverrideLazyIOBinder({ class WithSerialTLIOCells extends OverrideIOBinder({ (system: CanHavePeripheryTLSerial) => { - val (ports, cells) = system.serial_tl.zipWithIndex.map({ case (s, id) => + val (ports, cells) = system.serial_tls.zipWithIndex.map({ case (s, id) => val sys = system.asInstanceOf[BaseSubsystem] - val (port, cells) = IOCell.generateIOFromSignal(s.getWrappedValue, "serial_tl", sys.p(IOCellKey), abstractResetAsAsync = true) - (SerialTLPort(() => port, sys.p(SerialTLKey).get, system.serdesser.get, id), cells) + val (port, cells) = IOCell.generateIOFromSignal(s.getWrappedValue, s"serial_tl_$id", sys.p(IOCellKey), abstractResetAsAsync = true) + (SerialTLPort(() => port, sys.p(SerialTLKey)(id), system.serdessers(id), id), cells) }).unzip (ports.toSeq, cells.flatten.toSeq) } @@ -345,11 +345,11 @@ class WithSerialTLIOCells extends OverrideIOBinder({ class WithSerialTLPunchthrough extends OverrideIOBinder({ (system: CanHavePeripheryTLSerial) => { - val (ports, cells) = system.serial_tl.zipWithIndex.map({ case (s, id) => + val (ports, cells) = system.serial_tls.zipWithIndex.map({ case (s, id) => val sys = system.asInstanceOf[BaseSubsystem] val port = IO(chiselTypeOf(s.getWrappedValue)) port <> s.getWrappedValue - (SerialTLPort(() => port, sys.p(SerialTLKey).get, system.serdesser.get, id), Nil) + (SerialTLPort(() => port, sys.p(SerialTLKey)(id), system.serdessers(id), id), Nil) }).unzip (ports.toSeq, cells.flatten.toSeq) } diff --git a/generators/constellation b/generators/constellation index 03ed9e4e..3632183f 160000 --- a/generators/constellation +++ b/generators/constellation @@ -1 +1 @@ -Subproject commit 03ed9e4ecd31d71d4bd48f02b0e806bc2b8a7e6b +Subproject commit 3632183fd1171d00c7f78b32c305841d231031b7 diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index e4169ec2..ad643deb 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -69,7 +69,7 @@ class WithTSIBridgeAndHarnessRAMOverSerialTL extends HarnessBinder({ case (th: FireSim, port: SerialTLPort) => { val bits = port.io.bits port.io.clock := th.harnessBinderClock - val ram = LazyModule(new SerialRAM(port.serdesser)(Parameters.empty)) + val ram = LazyModule(new SerialRAM(port.serdesser, port.params)(port.serdesser.p)) Module(ram.module) ram.module.io.ser <> port.io.bits @@ -78,7 +78,7 @@ class WithTSIBridgeAndHarnessRAMOverSerialTL extends HarnessBinder({ // If FASED bridge is attached, loadmem widget is present val hasMainMemory = th.chipParameters(th.p(MultiChipIdx))(ExtMem).isDefined val mainMemoryName = Option.when(hasMainMemory)(MainMemoryConsts.globalName(th.p(MultiChipIdx))) - TSIBridge(th.harnessBinderClock, ram.module.io.tsi, mainMemoryName, th.harnessBinderReset.asBool)(th.p) + TSIBridge(th.harnessBinderClock, ram.module.io.tsi.get, mainMemoryName, th.harnessBinderReset.asBool)(th.p) } }) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index cf0ed66e..1b15374c 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -126,14 +126,14 @@ class WithFireSimHighPerfClocking extends Config( new chipyard.config.WithPeripheryBusFrequency(3200.0) ++ new chipyard.config.WithSystemBusFrequency(3200.0) ++ new chipyard.config.WithFrontBusFrequency(3200.0) ++ + new chipyard.config.WithControlBusFrequency(3200.0) ++ // Optional: These three configs put the DRAM memory system in it's own clock domain. // Removing the first config will result in the FASED timing model running // at the pbus freq (above, 3.2 GHz), which is outside the range of valid DDR3 speedgrades. // 1 GHz matches the FASED default, using some other frequency will require // runnings the FASED runtime configuration generator to generate faithful DDR3 timing values. new chipyard.config.WithMemoryBusFrequency(1000.0) ++ - new chipyard.config.WithAsynchrousMemoryBusCrossing ++ - new testchipip.WithAsynchronousSerialSlaveCrossing + new chipyard.config.WithAsynchrousMemoryBusCrossing ) // Tweaks that are generally applied to all firesim configs setting a single clock domain at 1000 MHz @@ -142,8 +142,10 @@ class WithFireSimConfigTweaks extends Config( // Using some other frequency will require runnings the FASED runtime configuration generator // to generate faithful DDR3 timing values. new chipyard.config.WithSystemBusFrequency(1000.0) ++ + new chipyard.config.WithControlBusFrequency(1000.0) ++ new chipyard.config.WithPeripheryBusFrequency(1000.0) ++ new chipyard.config.WithMemoryBusFrequency(1000.0) ++ + new chipyard.config.WithFrontBusFrequency(1000.0) ++ new WithFireSimDesignTweaks ) @@ -189,13 +191,14 @@ class WithFireSimTestChipConfigTweaks extends Config( new chipyard.config.WithSystemBusFrequency(500.0) ++ // Realistic system bus frequency new chipyard.config.WithMemoryBusFrequency(1000.0) ++ // Needs to be 1000 MHz to model DDR performance accurately new chipyard.config.WithPeripheryBusFrequency(500.0) ++ // Match the sbus and pbus frequency + new chipyard.config.WithFrontBusFrequency(500.0) ++ // Match the sbus and fbus frequency + new chipyard.config.WithControlBusFrequency(500.0) ++ // Match the sbus and cbus frequency new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "pbus", "fbus", "cbus", "implicit"), Seq("tile"))) ++ // Crossing specifications new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS new freechips.rocketchip.subsystem.WithRationalRocketTiles ++ // Add rational crossings between RocketTile and uncore new boom.common.WithRationalBoomTiles ++ // Add rational crossings between BoomTile and uncore - new testchipip.WithAsynchronousSerialSlaveCrossing ++ // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS new WithFireSimDesignTweaks ) @@ -250,10 +253,17 @@ class FireSimSmallSystemConfig extends Config( new WithDefaultMemModel ++ new WithBootROM ++ new chipyard.config.WithPeripheryBusFrequency(3200.0) ++ + new chipyard.config.WithControlBusFrequency(3200.0) ++ + new chipyard.config.WithSystemBusFrequency(3200.0) ++ + new chipyard.config.WithFrontBusFrequency(3200.0) ++ + new chipyard.config.WithMemoryBusFrequency(3200.0) ++ new WithoutClockGating ++ new WithoutTLMonitors ++ new freechips.rocketchip.subsystem.WithExtMemSize(1 << 28) ++ - new testchipip.WithDefaultSerialTL ++ + new testchipip.WithSerialTL(Seq(testchipip.SerialTLParams( + client = Some(testchipip.SerialTLClientParams(idBits = 4)), + width = 32 + ))) ++ new testchipip.WithBlockDevice ++ new chipyard.config.WithUARTInitBaudRate(BigInt(3686400L)) ++ new freechips.rocketchip.subsystem.WithInclusiveCache(nWays = 2, capacityKB = 64) ++ diff --git a/generators/testchipip b/generators/testchipip index c4c0774f..50a05b07 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit c4c0774f5ff7a407dd81e5f0b4289a2fdd9e8d63 +Subproject commit 50a05b078295f91798bee9d506a47a4e967dd493 diff --git a/scripts/build-toolchain-extra.sh b/scripts/build-toolchain-extra.sh index cc69ae1d..28cc9dfa 100755 --- a/scripts/build-toolchain-extra.sh +++ b/scripts/build-toolchain-extra.sh @@ -125,4 +125,10 @@ cd generators/testchipip/uart_tsi make cp uart_tsi $RISCV/bin +echo '==> Installing spike-devices' +cd $RDIR +git submodule update --init toolchains/riscv-tools/riscv-spike-devices +cd toolchains/riscv-tools/riscv-spike-devices +make install + echo "Extra Toolchain Utilities/Tests Build Complete!" diff --git a/scripts/replace-content.py b/scripts/replace-content.py index 4699ccca..a20acaa8 100755 --- a/scripts/replace-content.py +++ b/scripts/replace-content.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python +#!/usr/bin/env python3 # Replace text in a file given a key identifying a block to replace. # If the file doesn't exist, create it. diff --git a/toolchains/riscv-tools/riscv-isa-sim b/toolchains/riscv-tools/riscv-isa-sim index 5a499ef7..4d8651be 160000 --- a/toolchains/riscv-tools/riscv-isa-sim +++ b/toolchains/riscv-tools/riscv-isa-sim @@ -1 +1 @@ -Subproject commit 5a499ef718bba2fc323e9771ebd7545c66825ff6 +Subproject commit 4d8651be943ea706eb8dcb3443add2e7ccc117a6 diff --git a/toolchains/riscv-tools/riscv-spike-devices b/toolchains/riscv-tools/riscv-spike-devices new file mode 160000 index 00000000..8b4836db --- /dev/null +++ b/toolchains/riscv-tools/riscv-spike-devices @@ -0,0 +1 @@ +Subproject commit 8b4836db0b5b4ed0a9bab34e7707fe40c7c014be diff --git a/vlsi/example-designs/sky130-openroad-rockettile.yml b/vlsi/example-designs/sky130-openroad-rockettile.yml index c7300f9b..4a6b664c 100644 --- a/vlsi/example-designs/sky130-openroad-rockettile.yml +++ b/vlsi/example-designs/sky130-openroad-rockettile.yml @@ -22,27 +22,16 @@ vlsi.inputs.placement_constraints: bottom: 10 # Place SRAM memory instances - # SRAM paths and configurations are slightly different due to ENABLE_YOSYS_FLOW flag - # data cache - - path: "RocketTile/dcache/data/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0" + # data cache + - path: "RocketTile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0" type: hardmacro x: 50 y: 50 orientation: r90 - - path: "RocketTile/dcache/data/data_arrays_0_1/data_arrays_0_0_ext/mem_0_0" + - path: "RocketTile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_1_0" type: hardmacro x: 50 - y: 450 - orientation: r90 - - path: "RocketTile/dcache/data/data_arrays_0_2/data_arrays_0_0_ext/mem_0_0" - type: hardmacro - x: 50 - y: 850 - orientation: r90 - - path: "RocketTile/dcache/data/data_arrays_0_3/data_arrays_0_0_ext/mem_0_0" - type: hardmacro - x: 50 - y: 1250 + y: 800 orientation: r90 # tag array @@ -53,7 +42,7 @@ vlsi.inputs.placement_constraints: orientation: r90 # instruction cache - - path: "RocketTile/frontend/icache/data_arrays_0_0/data_arrays_0_0_0_ext/mem_0_0" + - path: "RocketTile/frontend/icache/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0" type: hardmacro x: 50 y: 2100 diff --git a/vlsi/example-designs/sky130-openroad.yml b/vlsi/example-designs/sky130-openroad.yml index 33f01cad..3b95d982 100644 --- a/vlsi/example-designs/sky130-openroad.yml +++ b/vlsi/example-designs/sky130-openroad.yml @@ -54,8 +54,6 @@ vlsi.inputs.placement_constraints: bottom: 10 # Place SRAM memory instances - # SRAM paths and configurations are slightly different due to ENABLE_YOSYS_FLOW flag - # data cache - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0" type: hardmacro x: 50 diff --git a/vlsi/example-sky130.yml b/vlsi/example-sky130.yml index 1cd281f7..1e3faf1c 100644 --- a/vlsi/example-sky130.yml +++ b/vlsi/example-sky130.yml @@ -48,6 +48,11 @@ vlsi.inputs.placement_constraints: x: 50 y: 50 orientation: r90 + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_1_0" + type: hardmacro + x: 50 + y: 800 + orientation: r90 # tag array - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0" diff --git a/vlsi/tutorial.mk b/vlsi/tutorial.mk index 92ba0a98..5e57455f 100644 --- a/vlsi/tutorial.mk +++ b/vlsi/tutorial.mk @@ -39,7 +39,6 @@ ifeq ($(tutorial),sky130-openroad) example-designs/sky130-openroad-rockettile.yml, ) VLSI_OBJ_DIR ?= build-sky130-openroad INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONFS) $(EXTRA_CONFS) - # Yosys compatibility for CIRCT-generated Verilog, at the expense of elaboration time. + # Yosys compatibility for CIRCT-generated Verilog ENABLE_YOSYS_FLOW = 1 endif -