wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Implement cosim purely in a HarnessBindeR

Browse Source
This commit is contained in:
Jerry Zhao
2023-02-05 20:59:14 -08:00
parent fc611ef507
commit 2a2de5850f
5 changed files with 12 additions and 24 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
generators/chipyard/src/main/scala/Cospike.scala
View File

@@ -32,22 +32,6 @@ class CospikeResources(
addResource("/vsrc/cospike.v")
}
case object SpikeCosimKey extends Field[Boolean](false)
trait CanHaveSpikeCosim { this: ChipyardSystem =>
if (p(SpikeCosimKey)) {
InModuleBody {
val isa = tiles.headOption.map(_.isaDTS).getOrElse("")
val mem0_base = p(ExtMem).map(_.master.base).getOrElse(BigInt(0))
val mem0_size = p(ExtMem).map(_.master.size).getOrElse(BigInt(0))
val pmpregions = tiles.headOption.map(_.tileParams.core.nPMPs).getOrElse(0)
val nharts = tiles.size
val bootrom = bootROM.map(_.module.contents.toArray.mkString(" ")).getOrElse("")
val resources = Module(new CospikeResources(isa, pmpregions, mem0_base, mem0_size, nharts, bootrom))
}
}
}
class SpikeCosim extends BlackBox with HasBlackBoxResource
{
addResource("/csrc/cospike.cc")

1
generators/chipyard/src/main/scala/DigitalTop.scala
View File

@@ -34,7 +34,6 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem
with chipyard.clocking.HasChipyardPRCI // Use Chipyard reset/clock distribution
with fftgenerator.CanHavePeripheryFFT // Enables optionally having an MMIO-based FFT block
with constellation.soc.CanHaveGlobalNoC // Support instantiating a global NoC interconnect
with chipyard.CanHaveSpikeCosim // Support instantiating spike-based co-simulation
{
override lazy val module = new DigitalTopModule(this)
}

12
generators/chipyard/src/main/scala/HarnessBinders.scala
View File

@@ -333,8 +333,18 @@ class WithSimDromajoBridge extends ComposeHarnessBinder({
}
})
class WithCospikeBridge extends ComposeHarnessBinder({
class WithCospike extends ComposeHarnessBinder({
(system: CanHaveTraceIOModuleImp, th: HasHarnessSignalReferences, ports: Seq[TraceOutputTop]) => {
implicit val p = chipyard.iobinders.GetSystemParameters(system)
val chipyardSystem = system.asInstanceOf[ChipyardSystemModule[_]].outer.asInstanceOf[ChipyardSystem]
val tiles = chipyardSystem.tiles
val isa = tiles.headOption.map(_.isaDTS).getOrElse("")
val mem0_base = p(ExtMem).map(_.master.base).getOrElse(BigInt(0))
val mem0_size = p(ExtMem).map(_.master.size).getOrElse(BigInt(0))
val pmpregions = tiles.headOption.map(_.tileParams.core.nPMPs).getOrElse(0)
val nharts = tiles.size
val bootrom = chipyardSystem.bootROM.map(_.module.contents.toArray.mkString(" ")).getOrElse("")
val resources = Module(new CospikeResources(isa, pmpregions, mem0_base, mem0_size, nharts, bootrom))
ports.map { p => p.traces.zipWithIndex.map(t => SpikeCosim(t._1, t._2)) }
}
})

3
generators/chipyard/src/main/scala/config/BoomConfigs.scala
View File

@@ -56,8 +56,7 @@ class DromajoBoomConfig extends Config(
new chipyard.config.AbstractConfig)
class MediumBoomCosimConfig extends Config(
new chipyard.harness.WithCospikeBridge ++ // attach spike-cosim
new chipyard.config.EnableSpikeCosim ++ // enable co-sim
new chipyard.harness.WithCospike ++ // attach spike-cosim
new chipyard.config.WithTraceIO ++ // enable the traceio
new boom.common.WithNMediumBooms(1) ++
new chipyard.config.AbstractConfig)

4
generators/chipyard/src/main/scala/config/fragments/TileFragments.scala
View File

@@ -9,7 +9,6 @@ import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams
import boom.common.{BoomTileAttachParams}
import cva6.{CVA6TileAttachParams}
import chipyard.{SpikeCosimKey}
import testchipip._
class WithL2TLBs(entries: Int) extends Config((site, here, up) => {
@@ -80,6 +79,3 @@ class WithRocketDCacheScratchpad extends Config((site, here, up) => {
}
})
class EnableSpikeCosim extends Config((site, here, up) => {
case SpikeCosimKey => true
})