From 2a2de5850f03cc76516ea827a7e563ff6dbe8ad5 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sun, 5 Feb 2023 20:59:14 -0800 Subject: [PATCH] Implement cosim purely in a HarnessBindeR --- generators/chipyard/src/main/scala/Cospike.scala | 16 ---------------- .../chipyard/src/main/scala/DigitalTop.scala | 1 - .../chipyard/src/main/scala/HarnessBinders.scala | 12 +++++++++++- .../src/main/scala/config/BoomConfigs.scala | 3 +-- .../scala/config/fragments/TileFragments.scala | 4 ---- 5 files changed, 12 insertions(+), 24 deletions(-) diff --git a/generators/chipyard/src/main/scala/Cospike.scala b/generators/chipyard/src/main/scala/Cospike.scala index 7adf3030..14eb018d 100644 --- a/generators/chipyard/src/main/scala/Cospike.scala +++ b/generators/chipyard/src/main/scala/Cospike.scala @@ -32,22 +32,6 @@ class CospikeResources( addResource("/vsrc/cospike.v") } -case object SpikeCosimKey extends Field[Boolean](false) - -trait CanHaveSpikeCosim { this: ChipyardSystem => - if (p(SpikeCosimKey)) { - InModuleBody { - val isa = tiles.headOption.map(_.isaDTS).getOrElse("") - val mem0_base = p(ExtMem).map(_.master.base).getOrElse(BigInt(0)) - val mem0_size = p(ExtMem).map(_.master.size).getOrElse(BigInt(0)) - val pmpregions = tiles.headOption.map(_.tileParams.core.nPMPs).getOrElse(0) - val nharts = tiles.size - val bootrom = bootROM.map(_.module.contents.toArray.mkString(" ")).getOrElse("") - val resources = Module(new CospikeResources(isa, pmpregions, mem0_base, mem0_size, nharts, bootrom)) - } - } -} - class SpikeCosim extends BlackBox with HasBlackBoxResource { addResource("/csrc/cospike.cc") diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index dc01d200..2777ba36 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -34,7 +34,6 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem with chipyard.clocking.HasChipyardPRCI // Use Chipyard reset/clock distribution with fftgenerator.CanHavePeripheryFFT // Enables optionally having an MMIO-based FFT block with constellation.soc.CanHaveGlobalNoC // Support instantiating a global NoC interconnect - with chipyard.CanHaveSpikeCosim // Support instantiating spike-based co-simulation { override lazy val module = new DigitalTopModule(this) } diff --git a/generators/chipyard/src/main/scala/HarnessBinders.scala b/generators/chipyard/src/main/scala/HarnessBinders.scala index 627644c3..f8e94044 100644 --- a/generators/chipyard/src/main/scala/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/HarnessBinders.scala @@ -333,8 +333,18 @@ class WithSimDromajoBridge extends ComposeHarnessBinder({ } }) -class WithCospikeBridge extends ComposeHarnessBinder({ +class WithCospike extends ComposeHarnessBinder({ (system: CanHaveTraceIOModuleImp, th: HasHarnessSignalReferences, ports: Seq[TraceOutputTop]) => { + implicit val p = chipyard.iobinders.GetSystemParameters(system) + val chipyardSystem = system.asInstanceOf[ChipyardSystemModule[_]].outer.asInstanceOf[ChipyardSystem] + val tiles = chipyardSystem.tiles + val isa = tiles.headOption.map(_.isaDTS).getOrElse("") + val mem0_base = p(ExtMem).map(_.master.base).getOrElse(BigInt(0)) + val mem0_size = p(ExtMem).map(_.master.size).getOrElse(BigInt(0)) + val pmpregions = tiles.headOption.map(_.tileParams.core.nPMPs).getOrElse(0) + val nharts = tiles.size + val bootrom = chipyardSystem.bootROM.map(_.module.contents.toArray.mkString(" ")).getOrElse("") + val resources = Module(new CospikeResources(isa, pmpregions, mem0_base, mem0_size, nharts, bootrom)) ports.map { p => p.traces.zipWithIndex.map(t => SpikeCosim(t._1, t._2)) } } }) diff --git a/generators/chipyard/src/main/scala/config/BoomConfigs.scala b/generators/chipyard/src/main/scala/config/BoomConfigs.scala index 84011931..da224a9b 100644 --- a/generators/chipyard/src/main/scala/config/BoomConfigs.scala +++ b/generators/chipyard/src/main/scala/config/BoomConfigs.scala @@ -56,8 +56,7 @@ class DromajoBoomConfig extends Config( new chipyard.config.AbstractConfig) class MediumBoomCosimConfig extends Config( - new chipyard.harness.WithCospikeBridge ++ // attach spike-cosim - new chipyard.config.EnableSpikeCosim ++ // enable co-sim + new chipyard.harness.WithCospike ++ // attach spike-cosim new chipyard.config.WithTraceIO ++ // enable the traceio new boom.common.WithNMediumBooms(1) ++ new chipyard.config.AbstractConfig) diff --git a/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala b/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala index e0367b4d..f19759cb 100644 --- a/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala @@ -9,7 +9,6 @@ import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams import boom.common.{BoomTileAttachParams} import cva6.{CVA6TileAttachParams} -import chipyard.{SpikeCosimKey} import testchipip._ class WithL2TLBs(entries: Int) extends Config((site, here, up) => { @@ -80,6 +79,3 @@ class WithRocketDCacheScratchpad extends Config((site, here, up) => { } }) -class EnableSpikeCosim extends Config((site, here, up) => { - case SpikeCosimKey => true -})