diff --git a/build.sbt b/build.sbt
index 476893d6..c509aac8 100644
--- a/build.sbt
+++ b/build.sbt
@@ -4,4 +4,4 @@ version := "1.0"
 
 name := "testchip-example"
 
-scalaVersion := "2.11.7"
+scalaVersion := "2.11.12"
diff --git a/rocket-chip b/rocket-chip
index 69b48b62..8c6e7456 160000
--- a/rocket-chip
+++ b/rocket-chip
@@ -1 +1 @@
-Subproject commit 69b48b623ab8c37e822f29e4a4a74a4944b12bd0
+Subproject commit 8c6e7456531c4d7b846d0532b2b94805b26c9793
diff --git a/src/main/scala/example/Configs.scala b/src/main/scala/example/Configs.scala
index f7302e8f..ee733986 100644
--- a/src/main/scala/example/Configs.scala
+++ b/src/main/scala/example/Configs.scala
@@ -2,7 +2,7 @@ package example
 
 import chisel3._
 import freechips.rocketchip.config.{Parameters, Config}
-import freechips.rocketchip.coreplex.{WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32}
+import freechips.rocketchip.subsystem.{WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32}
 import freechips.rocketchip.diplomacy.{LazyModule, ValName}
 import freechips.rocketchip.devices.tilelink.BootROMParams
 import freechips.rocketchip.tile.XLen
diff --git a/src/main/scala/example/PWM.scala b/src/main/scala/example/PWM.scala
index e4fca0cb..c2621d3f 100644
--- a/src/main/scala/example/PWM.scala
+++ b/src/main/scala/example/PWM.scala
@@ -2,7 +2,7 @@ package example
 
 import chisel3._
 import chisel3.util._
-import freechips.rocketchip.coreplex.HasPeripheryBus
+import freechips.rocketchip.subsystem.BaseSubsystem
 import freechips.rocketchip.config.{Parameters, Field}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.regmapper.{HasRegMap, RegField}
@@ -71,15 +71,16 @@ class PWMTL(c: PWMParams)(implicit p: Parameters)
       new TLRegBundle(c, _) with PWMTLBundle)(
       new TLRegModule(c, _, _) with PWMTLModule)
 
-trait HasPeripheryPWM extends HasPeripheryBus {
+trait HasPeripheryPWM { this: BaseSubsystem =>
   implicit val p: Parameters
 
   private val address = 0x2000
+  private val portName = "pwm"
 
   val pwm = LazyModule(new PWMTL(
     PWMParams(address, pbus.beatBytes))(p))
 
-  pwm.node := pbus.toVariableWidthSlaves
+  pbus.toVariableWidthSlave(Some(portName)) { pwm.node }
 }
 
 trait HasPeripheryPWMModuleImp extends LazyModuleImp {
diff --git a/src/main/scala/example/Top.scala b/src/main/scala/example/Top.scala
index b0f9ba83..cf554a61 100644
--- a/src/main/scala/example/Top.scala
+++ b/src/main/scala/example/Top.scala
@@ -1,13 +1,13 @@
 package example
 
 import chisel3._
-import freechips.rocketchip.coreplex._
+import freechips.rocketchip.subsystem._
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.devices.tilelink._
 import freechips.rocketchip.util.DontTouch
 import testchipip._
 
-class ExampleTop(implicit p: Parameters) extends RocketCoreplex
+class ExampleTop(implicit p: Parameters) extends RocketSubsystem
     with HasMasterAXI4MemPort
     with HasPeripheryBootROM
     with HasSystemErrorSlave
@@ -17,7 +17,7 @@ class ExampleTop(implicit p: Parameters) extends RocketCoreplex
   override lazy val module = new ExampleTopModule(this)
 }
 
-class ExampleTopModule[+L <: ExampleTop](l: L) extends RocketCoreplexModule(l)
+class ExampleTopModule[+L <: ExampleTop](l: L) extends RocketSubsystemModuleImp(l)
     with HasRTCModuleImp
     with HasMasterAXI4MemPortModuleImp
     with HasPeripheryBootROMModuleImp
diff --git a/testchipip b/testchipip
index 693698bb..d21b2253 160000
--- a/testchipip
+++ b/testchipip
@@ -1 +1 @@
-Subproject commit 693698bb4b6f277958b2981c8ad69b90f84bb765
+Subproject commit d21b2253ec7efd754c47484359e3403e9519e0d9