From 235b1e5dfd33b4a980a80463aec72ea0bd7a8648 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 8 Feb 2021 09:03:15 -0800 Subject: [PATCH] Give TraceGenConfigs an explicit mbus clock --- generators/chipyard/src/main/scala/config/TracegenConfigs.scala | 2 ++ 1 file changed, 2 insertions(+) diff --git a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala index f9980bf6..3f9e27d1 100644 --- a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala +++ b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala @@ -11,6 +11,8 @@ class AbstractTraceGenConfig extends Config( new chipyard.config.WithTracegenSystem ++ new chipyard.config.WithNoSubsystemDrivenClocks ++ new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ + new chipyard.config.WithMemoryBusFrequency(100.0) ++ + new chipyard.config.WithPeripheryBusFrequency(100.0) ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.groundtest.GroundTestBaseConfig)