update to latest rocket-chip

This commit is contained in:
Howard Mao
2017-06-21 10:55:36 -07:00
parent 0d821efb5f
commit 1f3e892b64
6 changed files with 32 additions and 57 deletions

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@@ -14,13 +14,8 @@ class TestHarness(implicit val p: Parameters) extends Module {
def buildTop(p: Parameters): ExampleTop = LazyModule(new ExampleTop()(p)) def buildTop(p: Parameters): ExampleTop = LazyModule(new ExampleTop()(p))
val dut = Module(buildTop(p).module) val dut = Module(buildTop(p).module)
val ser = Module(new SimSerialWrapper(p(SerialInterfaceWidth))) dut.connectSimAXIMem()
io.success := dut.connectSimSerial()
val nMemChannels = p(coreplex.BankedL2Config).nMemoryChannels
val mem = Module(LazyModule(new SimAXIMem(nMemChannels)).module)
mem.io.axi4 <> dut.io.mem_axi4
ser.io.serial <> dut.io.serial
io.success := ser.io.exit
} }
object Generator extends GeneratorApp { object Generator extends GeneratorApp {

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@@ -5,34 +5,22 @@ import config.Parameters
import testchipip._ import testchipip._
import rocketchip._ import rocketchip._
class ExampleTop(implicit p: Parameters) extends BaseTop()(p) class ExampleTop(implicit p: Parameters) extends BaseSystem
with PeripheryMasterAXI4Mem with HasPeripheryMasterAXI4MemPort
with PeripheryBootROM with HasPeripheryErrorSlave
with PeripheryZero with HasPeripheryZeroSlave
with PeripheryCounter with HasPeripheryBootROM
with HardwiredResetVector with HasPeripheryRTCCounter
with RocketPlexMaster with HasRocketPlexMaster
with NoDebug with HasNoDebug
with PeripherySerial { with HasPeripherySerial {
override lazy val module = new ExampleTopModule(this, () => new ExampleTopBundle(this)) override lazy val module = new ExampleTopModule(this)
} }
class ExampleTopBundle[+L <: ExampleTop](l: L) extends BaseTopBundle(l) class ExampleTopModule[+L <: ExampleTop](l: L) extends BaseSystemModule(l)
with PeripheryMasterAXI4MemBundle with HasPeripheryMasterAXI4MemPortModuleImp
with PeripheryBootROMBundle with HasPeripheryBootROMModuleImp
with PeripheryZeroBundle with HasPeripheryRTCCounterModuleImp
with PeripheryCounterBundle with HasRocketPlexMasterModuleImp
with HardwiredResetVectorBundle with HasNoDebugModuleImp
with RocketPlexMasterBundle with HasPeripherySerialModuleImp
with PeripherySerialBundle
class ExampleTopModule[+L <: ExampleTop, +B <: ExampleTopBundle[L]](l: L, b: () => B)
extends BaseTopModule(l, b)
with PeripheryMasterAXI4MemModule
with PeripheryBootROMModule
with PeripheryZeroModule
with PeripheryCounterModule
with HardwiredResetVectorModule
with RocketPlexMasterModule
with NoDebugModule
with PeripherySerialModule

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@@ -76,9 +76,8 @@ class PWMTL(c: PWMParams)(implicit p: Parameters)
new TLRegBundle(c, _) with PWMTLBundle)( new TLRegBundle(c, _) with PWMTLBundle)(
new TLRegModule(c, _, _) with PWMTLModule) new TLRegModule(c, _, _) with PWMTLModule)
trait PeripheryPWM extends LazyModule with HasPeripheryParameters { trait HasPeripheryPWM extends HasSystemNetworks {
implicit val p: Parameters implicit val p: Parameters
val peripheryBus: TLXbar
private val address = 0x2000 private val address = 0x2000
@@ -89,14 +88,11 @@ trait PeripheryPWM extends LazyModule with HasPeripheryParameters {
peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node) peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
} }
trait PeripheryPWMBundle { trait HasPeripheryPWMModuleImp extends LazyMultiIOModuleImp {
val pwmout = Output(Bool())
}
trait PeripheryPWMModule extends HasPeripheryParameters {
implicit val p: Parameters implicit val p: Parameters
val io: PeripheryPWMBundle val outer: HasPeripheryPWM
val outer: PeripheryPWM
io.pwmout := outer.pwm.module.io.pwmout val pwmout = IO(Output(Bool()))
pwmout := outer.pwm.module.io.pwmout
} }

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@@ -4,14 +4,10 @@ import chisel3._
import example._ import example._
import config.Parameters import config.Parameters
class ExampleTopWithPWM(implicit p: Parameters) extends ExampleTop()(p) class ExampleTopWithPWM(implicit p: Parameters) extends ExampleTop
with PeripheryPWM { with HasPeripheryPWM {
override lazy val module = new ExampleTopWithPWMModule(this, () => new ExampleTopWithPWMBundle(this)) override lazy val module = new ExampleTopWithPWMModule(this)
} }
class ExampleTopWithPWMBundle[+L <: ExampleTopWithPWM](l: L) class ExampleTopWithPWMModule(l: ExampleTopWithPWM)
extends ExampleTopBundle(l) extends ExampleTopModule(l) with HasPeripheryPWMModuleImp
with PeripheryPWMBundle
class ExampleTopWithPWMModule[+L <: ExampleTopWithPWM, +B <: ExampleTopWithPWMBundle[L]](l: L, b: () => B)
extends ExampleTopModule(l, b) with PeripheryPWMModule