From 1f3e892b64278bd782a1fdb462b329b850fc4cd6 Mon Sep 17 00:00:00 2001
From: Howard Mao <zhehao.mao@gmail.com>
Date: Wed, 21 Jun 2017 10:55:36 -0700
Subject: [PATCH] update to latest rocket-chip

---
 rocket-chip                              |  2 +-
 src/main/scala/example/TestHarness.scala |  9 ++---
 src/main/scala/example/Top.scala         | 46 +++++++++---------------
 src/main/scala/pwm/PWM.scala             | 16 ++++-----
 src/main/scala/pwm/Top.scala             | 14 +++-----
 testchipip                               |  2 +-
 6 files changed, 32 insertions(+), 57 deletions(-)

diff --git a/rocket-chip b/rocket-chip
index 274d908d..0fdaa286 160000
--- a/rocket-chip
+++ b/rocket-chip
@@ -1 +1 @@
-Subproject commit 274d908d98617f928e47b192cc2f68a3f7ded512
+Subproject commit 0fdaa286942a96220e19658a0a8a80f8ce8fee5f
diff --git a/src/main/scala/example/TestHarness.scala b/src/main/scala/example/TestHarness.scala
index d5357622..5cfc67d1 100644
--- a/src/main/scala/example/TestHarness.scala
+++ b/src/main/scala/example/TestHarness.scala
@@ -14,13 +14,8 @@ class TestHarness(implicit val p: Parameters) extends Module {
   def buildTop(p: Parameters): ExampleTop = LazyModule(new ExampleTop()(p))
 
   val dut = Module(buildTop(p).module)
-  val ser = Module(new SimSerialWrapper(p(SerialInterfaceWidth)))
-
-  val nMemChannels = p(coreplex.BankedL2Config).nMemoryChannels
-  val mem = Module(LazyModule(new SimAXIMem(nMemChannels)).module)
-  mem.io.axi4 <> dut.io.mem_axi4
-  ser.io.serial <> dut.io.serial
-  io.success := ser.io.exit
+  dut.connectSimAXIMem()
+  io.success := dut.connectSimSerial()
 }
 
 object Generator extends GeneratorApp {
diff --git a/src/main/scala/example/Top.scala b/src/main/scala/example/Top.scala
index 1d5e5d85..fa90ad79 100644
--- a/src/main/scala/example/Top.scala
+++ b/src/main/scala/example/Top.scala
@@ -5,34 +5,22 @@ import config.Parameters
 import testchipip._
 import rocketchip._
 
-class ExampleTop(implicit p: Parameters) extends BaseTop()(p)
-    with PeripheryMasterAXI4Mem
-    with PeripheryBootROM
-    with PeripheryZero
-    with PeripheryCounter
-    with HardwiredResetVector
-    with RocketPlexMaster
-    with NoDebug
-    with PeripherySerial {
-  override lazy val module = new ExampleTopModule(this, () => new ExampleTopBundle(this))
+class ExampleTop(implicit p: Parameters) extends BaseSystem
+    with HasPeripheryMasterAXI4MemPort
+    with HasPeripheryErrorSlave
+    with HasPeripheryZeroSlave
+    with HasPeripheryBootROM
+    with HasPeripheryRTCCounter
+    with HasRocketPlexMaster
+    with HasNoDebug
+    with HasPeripherySerial {
+  override lazy val module = new ExampleTopModule(this)
 }
 
-class ExampleTopBundle[+L <: ExampleTop](l: L) extends BaseTopBundle(l)
-    with PeripheryMasterAXI4MemBundle
-    with PeripheryBootROMBundle
-    with PeripheryZeroBundle
-    with PeripheryCounterBundle
-    with HardwiredResetVectorBundle
-    with RocketPlexMasterBundle
-    with PeripherySerialBundle
-
-class ExampleTopModule[+L <: ExampleTop, +B <: ExampleTopBundle[L]](l: L, b: () => B)
-  extends BaseTopModule(l, b)
-    with PeripheryMasterAXI4MemModule
-    with PeripheryBootROMModule
-    with PeripheryZeroModule
-    with PeripheryCounterModule
-    with HardwiredResetVectorModule
-    with RocketPlexMasterModule
-    with NoDebugModule
-    with PeripherySerialModule
+class ExampleTopModule[+L <: ExampleTop](l: L) extends BaseSystemModule(l)
+    with HasPeripheryMasterAXI4MemPortModuleImp
+    with HasPeripheryBootROMModuleImp
+    with HasPeripheryRTCCounterModuleImp
+    with HasRocketPlexMasterModuleImp
+    with HasNoDebugModuleImp
+    with HasPeripherySerialModuleImp
diff --git a/src/main/scala/pwm/PWM.scala b/src/main/scala/pwm/PWM.scala
index b1a7748f..6fe9aced 100644
--- a/src/main/scala/pwm/PWM.scala
+++ b/src/main/scala/pwm/PWM.scala
@@ -76,9 +76,8 @@ class PWMTL(c: PWMParams)(implicit p: Parameters)
       new TLRegBundle(c, _) with PWMTLBundle)(
       new TLRegModule(c, _, _) with PWMTLModule)
 
-trait PeripheryPWM extends LazyModule with HasPeripheryParameters {
+trait HasPeripheryPWM extends HasSystemNetworks {
   implicit val p: Parameters
-  val peripheryBus: TLXbar
 
   private val address = 0x2000
 
@@ -89,14 +88,11 @@ trait PeripheryPWM extends LazyModule with HasPeripheryParameters {
     peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
 }
 
-trait PeripheryPWMBundle {
-  val pwmout = Output(Bool())
-}
-
-trait PeripheryPWMModule extends HasPeripheryParameters {
+trait HasPeripheryPWMModuleImp extends LazyMultiIOModuleImp {
   implicit val p: Parameters
-  val io: PeripheryPWMBundle
-  val outer: PeripheryPWM
+  val outer: HasPeripheryPWM
 
-  io.pwmout := outer.pwm.module.io.pwmout
+  val pwmout = IO(Output(Bool()))
+
+  pwmout := outer.pwm.module.io.pwmout
 }
diff --git a/src/main/scala/pwm/Top.scala b/src/main/scala/pwm/Top.scala
index 32add8fb..2e99007c 100644
--- a/src/main/scala/pwm/Top.scala
+++ b/src/main/scala/pwm/Top.scala
@@ -4,14 +4,10 @@ import chisel3._
 import example._
 import config.Parameters
 
-class ExampleTopWithPWM(implicit p: Parameters) extends ExampleTop()(p)
-    with PeripheryPWM {
-  override lazy val module = new ExampleTopWithPWMModule(this, () => new ExampleTopWithPWMBundle(this))
+class ExampleTopWithPWM(implicit p: Parameters) extends ExampleTop
+    with HasPeripheryPWM {
+  override lazy val module = new ExampleTopWithPWMModule(this)
 }
 
-class ExampleTopWithPWMBundle[+L <: ExampleTopWithPWM](l: L)
-  extends ExampleTopBundle(l)
-  with PeripheryPWMBundle
-
-class ExampleTopWithPWMModule[+L <: ExampleTopWithPWM, +B <: ExampleTopWithPWMBundle[L]](l: L, b: () => B)
-    extends ExampleTopModule(l, b) with PeripheryPWMModule
+class ExampleTopWithPWMModule(l: ExampleTopWithPWM)
+  extends ExampleTopModule(l) with HasPeripheryPWMModuleImp
diff --git a/testchipip b/testchipip
index 8bd439f3..2e9301c1 160000
--- a/testchipip
+++ b/testchipip
@@ -1 +1 @@
-Subproject commit 8bd439f37b0e80a045ab35558d044ca5020e7edd
+Subproject commit 2e9301c19012d7895abca7165296dd788893bccc