update to latest rocket-chip

This commit is contained in:
Howard Mao
2017-06-21 10:55:36 -07:00
parent 0d821efb5f
commit 1f3e892b64
6 changed files with 32 additions and 57 deletions

View File

@@ -14,13 +14,8 @@ class TestHarness(implicit val p: Parameters) extends Module {
def buildTop(p: Parameters): ExampleTop = LazyModule(new ExampleTop()(p))
val dut = Module(buildTop(p).module)
val ser = Module(new SimSerialWrapper(p(SerialInterfaceWidth)))
val nMemChannels = p(coreplex.BankedL2Config).nMemoryChannels
val mem = Module(LazyModule(new SimAXIMem(nMemChannels)).module)
mem.io.axi4 <> dut.io.mem_axi4
ser.io.serial <> dut.io.serial
io.success := ser.io.exit
dut.connectSimAXIMem()
io.success := dut.connectSimSerial()
}
object Generator extends GeneratorApp {