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Test with wider 128bit sbus in MemTraceCore

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This commit is contained in:
Hansung Kim
2023-07-22 12:58:28 -07:00
parent 9efd72ee2b
commit 1a4773ecaf
1 changed files with 4 additions and 4 deletions
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8
generators/chipyard/src/main/scala/config/GPUConfig.scala
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@@ -8,14 +8,14 @@ class MemtraceCoreConfig extends Config(
// Memtrace
new freechips.rocketchip.subsystem.WithMemtraceCore("vecadd.core1.thread4.trace",
traceHasSource = false) ++
// new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.trace",
// new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace",
// traceHasSource = false) ++
new freechips.rocketchip.subsystem.WithCoalescer() ++
new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=4) ++
new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds = 2) ++
new freechips.rocketchip.subsystem.WithSimtLanes(nLanes = 4, nSrcIds = 8) ++
// L2
new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
new freechips.rocketchip.subsystem.WithNBanks(4) ++
new chipyard.config.WithSystemBusWidth(64) ++
new chipyard.config.WithSystemBusWidth(16 * 8) ++
// Small Rocket core that does nothing
new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++
new chipyard.config.AbstractConfig