From 1a4773ecaf32409194c79f22973a421bbd6c8dda Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Sat, 22 Jul 2023 12:58:28 -0700 Subject: [PATCH] Test with wider 128bit sbus in MemTraceCore --- generators/chipyard/src/main/scala/config/GPUConfig.scala | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/GPUConfig.scala b/generators/chipyard/src/main/scala/config/GPUConfig.scala index 9565c9c0..2a727a0f 100644 --- a/generators/chipyard/src/main/scala/config/GPUConfig.scala +++ b/generators/chipyard/src/main/scala/config/GPUConfig.scala @@ -8,14 +8,14 @@ class MemtraceCoreConfig extends Config( // Memtrace new freechips.rocketchip.subsystem.WithMemtraceCore("vecadd.core1.thread4.trace", traceHasSource = false) ++ - // new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.trace", + // new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace", // traceHasSource = false) ++ - new freechips.rocketchip.subsystem.WithCoalescer() ++ - new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=4) ++ + new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds = 2) ++ + new freechips.rocketchip.subsystem.WithSimtLanes(nLanes = 4, nSrcIds = 8) ++ // L2 new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++ new freechips.rocketchip.subsystem.WithNBanks(4) ++ - new chipyard.config.WithSystemBusWidth(64) ++ + new chipyard.config.WithSystemBusWidth(16 * 8) ++ // Small Rocket core that does nothing new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++ new chipyard.config.AbstractConfig