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RegInit is no longer in util (#14)

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edwardcwang
2017-03-14 23:24:31 -07:00
committed by Angie Wang
parent 4745d29912
commit 164bf2152c
1 changed files with 1 additions and 2 deletions
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3
tapeout/src/main/scala/transforms/clkgen/ClkDivider.scala
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@@ -2,7 +2,6 @@ package barstools.tapeout.transforms.clkgen
import chisel3.experimental.{withClockAndReset, withClock, withReset} import chisel3.experimental.{withClockAndReset, withClock, withReset}
import chisel3._ import chisel3._
import chisel3.util.RegInit
import barstools.tapeout.transforms._ import barstools.tapeout.transforms._
import chisel3.util.HasBlackBoxInline import chisel3.util.HasBlackBoxInline
@@ -125,4 +124,4 @@ class SEClkDivider(divBy: Int, phases: Seq[Int], analogFile: String = "", syncRe
} }
else throw new Exception("Clock divider Verilog file invalid!") else throw new Exception("Clock divider Verilog file invalid!")
} }
} }