From 164bf2152c37430bcbc1b4c39c66920d6896ed66 Mon Sep 17 00:00:00 2001
From: edwardcwang <edwardcwang@users.noreply.github.com>
Date: Tue, 14 Mar 2017 23:24:31 -0700
Subject: [PATCH] RegInit is no longer in util (#14)

---
 tapeout/src/main/scala/transforms/clkgen/ClkDivider.scala | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/tapeout/src/main/scala/transforms/clkgen/ClkDivider.scala b/tapeout/src/main/scala/transforms/clkgen/ClkDivider.scala
index 755a66aa..3f41a128 100644
--- a/tapeout/src/main/scala/transforms/clkgen/ClkDivider.scala
+++ b/tapeout/src/main/scala/transforms/clkgen/ClkDivider.scala
@@ -2,7 +2,6 @@ package barstools.tapeout.transforms.clkgen
 
 import chisel3.experimental.{withClockAndReset, withClock, withReset}
 import chisel3._
-import chisel3.util.RegInit
 import barstools.tapeout.transforms._
 import chisel3.util.HasBlackBoxInline
 
@@ -125,4 +124,4 @@ class SEClkDivider(divBy: Int, phases: Seq[Int], analogFile: String = "", syncRe
       }
       else throw new Exception("Clock divider Verilog file invalid!")
   }
-}
\ No newline at end of file
+}