diff --git a/tapeout/src/main/scala/transforms/clkgen/ClkDivider.scala b/tapeout/src/main/scala/transforms/clkgen/ClkDivider.scala
index 755a66aa..3f41a128 100644
--- a/tapeout/src/main/scala/transforms/clkgen/ClkDivider.scala
+++ b/tapeout/src/main/scala/transforms/clkgen/ClkDivider.scala
@@ -2,7 +2,6 @@ package barstools.tapeout.transforms.clkgen
 
 import chisel3.experimental.{withClockAndReset, withClock, withReset}
 import chisel3._
-import chisel3.util.RegInit
 import barstools.tapeout.transforms._
 import chisel3.util.HasBlackBoxInline
 
@@ -125,4 +124,4 @@ class SEClkDivider(divBy: Int, phases: Seq[Int], analogFile: String = "", syncRe
       }
       else throw new Exception("Clock divider Verilog file invalid!")
   }
-}
\ No newline at end of file
+}