make sure annotations are generated and carried through to verilog elaboration

This commit is contained in:
Howard Mao
2018-02-23 11:50:33 -08:00
parent 1dfe9b1c9f
commit 073c16961e
3 changed files with 9 additions and 4 deletions

View File

@@ -22,4 +22,5 @@ class TestHarness(implicit val p: Parameters) extends Module {
object Generator extends GeneratorApp {
generateFirrtl
generateAnno
}