From 073c16961e91dad1c119286dfc0e737730ae6f9c Mon Sep 17 00:00:00 2001
From: Howard Mao <zhehao.mao@gmail.com>
Date: Fri, 23 Feb 2018 11:50:33 -0800
Subject: [PATCH] make sure annotations are generated and carried through to
 verilog elaboration

---
 Makefrag                                 | 10 +++++++---
 src/main/scala/example/TestHarness.scala |  1 +
 testchipip                               |  2 +-
 3 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/Makefrag b/Makefrag
index 6e138e75..1734a205 100644
--- a/Makefrag
+++ b/Makefrag
@@ -36,9 +36,13 @@ bootrom_img = $(base_dir)/bootrom/bootrom.rv64.img $(base_dir)/bootrom/bootrom.r
 
 CHISEL_ARGS ?=
 
-$(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).fir: $(rocketchip_stamp) $(extra_stamps) $(call lookup_scala_srcs,$(base_dir)/src/main/scala) $(bootrom_img)
+FIRRTL_FILE=$(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).fir
+ANNO_FILE=$(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).anno
+VERILOG_FILE=$(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).v
+
+$(FIRRTL_FILE) $(ANNO_FILE): $(rocketchip_stamp) $(extra_stamps) $(call lookup_scala_srcs,$(base_dir)/src/main/scala) $(bootrom_img)
 	mkdir -p $(build_dir)
 	cd $(base_dir) && $(SBT) "runMain $(PROJECT).Generator $(CHISEL_ARGS) $(build_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
 
-$(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).v: $(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).fir $(FIRRTL_JAR)
-	$(FIRRTL) -i $< -o $@ -X verilog
+$(VERILOG_FILE): $(FIRRTL_FILE) $(ANNO_FILE) $(FIRRTL_JAR)
+	$(FIRRTL) -i $(FIRRTL_FILE) -o $(VERILOG_FILE) -X verilog -faf $(ANNO_FILE)
diff --git a/src/main/scala/example/TestHarness.scala b/src/main/scala/example/TestHarness.scala
index ecda7047..e67a1899 100644
--- a/src/main/scala/example/TestHarness.scala
+++ b/src/main/scala/example/TestHarness.scala
@@ -22,4 +22,5 @@ class TestHarness(implicit val p: Parameters) extends Module {
 
 object Generator extends GeneratorApp {
   generateFirrtl
+  generateAnno
 }
diff --git a/testchipip b/testchipip
index 3cd6ece8..693698bb 160000
--- a/testchipip
+++ b/testchipip
@@ -1 +1 @@
-Subproject commit 3cd6ece8739eb228a5c345a7e6b826540dfb79b0
+Subproject commit 693698bb4b6f277958b2981c8ad69b90f84bb765