146 lines
3.6 KiB
Scala
146 lines
3.6 KiB
Scala
import chisel3._
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import chisel3.util._
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class FetchPacket(p: CoreParams = CoreParams()) extends Bundle {
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val pc = UInt(p.xlen.W)
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val inst = Vec(p.fetchWidth, UInt(32.W))
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val laneValid = Vec(p.fetchWidth, Bool())
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val predictedTaken = Bool()
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val predictedTarget = UInt(p.xlen.W)
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}
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class BranchUpdate(p: CoreParams = CoreParams()) extends Bundle {
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val valid = Bool()
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val pc = UInt(p.xlen.W)
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val taken = Bool()
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val target = UInt(p.xlen.W)
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val isCall = Bool()
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val isReturn = Bool()
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}
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class DecodedInst(p: CoreParams = CoreParams()) extends Bundle {
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val valid = Bool()
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val pc = UInt(p.xlen.W)
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val inst = UInt(32.W)
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val rs1 = UInt(5.W)
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val rs2 = UInt(5.W)
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val rd = UInt(5.W)
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val funct3 = UInt(3.W)
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val funct7 = UInt(7.W)
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val immI = UInt(p.xlen.W)
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val immS = UInt(p.xlen.W)
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val immB = UInt(p.xlen.W)
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val immU = UInt(p.xlen.W)
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val immJ = UInt(p.xlen.W)
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val opClass = UInt(Consts.OpClassWidth.W)
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val aluFn = UInt(5.W)
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val memWidth = UInt(3.W)
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val memSigned = Bool()
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val isLoad = Bool()
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val isStore = Bool()
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val isBranch = Bool()
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val isJal = Bool()
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val isJalr = Bool()
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val isLui = Bool()
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val isAuipc = Bool()
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val isOpImm = Bool()
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val isOp = Bool()
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val isWord = Bool()
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val isSystem = Bool()
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val isFenceI = Bool()
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val isAmo = Bool()
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val amoOp = UInt(5.W)
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val writesRd = Bool()
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val illegal = Bool()
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}
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class RenamePacket(p: CoreParams = CoreParams()) extends Bundle {
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val valid = Bool()
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val decoded = new DecodedInst(p)
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val prs1 = UInt(log2Ceil(p.physRegs).W)
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val prs2 = UInt(log2Ceil(p.physRegs).W)
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val src1Ready = Bool()
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val src2Ready = Bool()
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val prd = UInt(log2Ceil(p.physRegs).W)
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val oldPrd = UInt(log2Ceil(p.physRegs).W)
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val robIdx = UInt(log2Ceil(p.robEntries).W)
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}
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class Wakeup(p: CoreParams = CoreParams()) extends Bundle {
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val valid = Bool()
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val phys = UInt(log2Ceil(p.physRegs).W)
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val data = UInt(p.xlen.W)
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}
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class MemRequest(p: CoreParams = CoreParams()) extends Bundle {
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val addr = UInt(p.xlen.W)
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val data = UInt(p.xlen.W)
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val isStore = Bool()
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val isSigned = Bool()
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val isAmo = Bool()
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val amoOp = UInt(5.W)
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val size = UInt(3.W)
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}
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class CsrCommand(p: CoreParams = CoreParams()) extends Bundle {
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val valid = Bool()
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val addr = UInt(12.W)
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val cmd = UInt(3.W)
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val rs1 = UInt(p.xlen.W)
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val zimm = UInt(5.W)
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}
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class TlbReq(p: CoreParams = CoreParams()) extends Bundle {
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val valid = Bool()
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val vaddr = UInt(p.xlen.W)
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val isStore = Bool()
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val isFetch = Bool()
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}
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class TlbResp(p: CoreParams = CoreParams()) extends Bundle {
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val hit = Bool()
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val miss = Bool()
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val paddr = UInt(p.xlen.W)
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val pageFault = Bool()
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val accessFault = Bool()
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}
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class TlbRefill(p: CoreParams = CoreParams()) extends Bundle {
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val valid = Bool()
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val vpn = UInt(27.W)
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val ppn = UInt(44.W)
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val level = UInt(2.W)
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val flags = UInt(8.W)
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}
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class PtwMemReq(p: CoreParams = CoreParams()) extends Bundle {
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val valid = Bool()
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val addr = UInt(p.xlen.W)
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}
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class PtwMemResp(p: CoreParams = CoreParams()) extends Bundle {
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val valid = Bool()
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val data = UInt(p.xlen.W)
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}
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class LoadQueueEntry(p: CoreParams = CoreParams()) extends Bundle {
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val valid = Bool()
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val robIdx = UInt(log2Ceil(p.robEntries).W)
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val addrValid = Bool()
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val addr = UInt(p.xlen.W)
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val size = UInt(3.W)
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val completed = Bool()
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val violation = Bool()
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}
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class StoreQueueEntry(p: CoreParams = CoreParams()) extends Bundle {
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val valid = Bool()
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val robIdx = UInt(log2Ceil(p.robEntries).W)
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val addrValid = Bool()
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val dataValid = Bool()
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val addr = UInt(p.xlen.W)
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val data = UInt(p.xlen.W)
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val size = UInt(3.W)
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val committed = Bool()
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}
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