import chisel3._
import chisel3.util._

class FetchPacket(p: CoreParams = CoreParams()) extends Bundle {
  val pc = UInt(p.xlen.W)
  val inst = Vec(p.fetchWidth, UInt(32.W))
  val laneValid = Vec(p.fetchWidth, Bool())
  val predictedTaken = Bool()
  val predictedTarget = UInt(p.xlen.W)
}

class BranchUpdate(p: CoreParams = CoreParams()) extends Bundle {
  val valid = Bool()
  val pc = UInt(p.xlen.W)
  val taken = Bool()
  val target = UInt(p.xlen.W)
  val isCall = Bool()
  val isReturn = Bool()
}

class DecodedInst(p: CoreParams = CoreParams()) extends Bundle {
  val valid = Bool()
  val pc = UInt(p.xlen.W)
  val inst = UInt(32.W)
  val rs1 = UInt(5.W)
  val rs2 = UInt(5.W)
  val rd = UInt(5.W)
  val funct3 = UInt(3.W)
  val funct7 = UInt(7.W)
  val immI = UInt(p.xlen.W)
  val immS = UInt(p.xlen.W)
  val immB = UInt(p.xlen.W)
  val immU = UInt(p.xlen.W)
  val immJ = UInt(p.xlen.W)
  val opClass = UInt(Consts.OpClassWidth.W)
  val aluFn = UInt(5.W)
  val memWidth = UInt(3.W)
  val memSigned = Bool()
  val isLoad = Bool()
  val isStore = Bool()
  val isBranch = Bool()
  val isJal = Bool()
  val isJalr = Bool()
  val isLui = Bool()
  val isAuipc = Bool()
  val isOpImm = Bool()
  val isOp = Bool()
  val isWord = Bool()
  val isSystem = Bool()
  val isFenceI = Bool()
  val isAmo = Bool()
  val amoOp = UInt(5.W)
  val writesRd = Bool()
  val illegal = Bool()
}

class RenamePacket(p: CoreParams = CoreParams()) extends Bundle {
  val valid = Bool()
  val decoded = new DecodedInst(p)
  val prs1 = UInt(log2Ceil(p.physRegs).W)
  val prs2 = UInt(log2Ceil(p.physRegs).W)
  val src1Ready = Bool()
  val src2Ready = Bool()
  val prd = UInt(log2Ceil(p.physRegs).W)
  val oldPrd = UInt(log2Ceil(p.physRegs).W)
  val robIdx = UInt(log2Ceil(p.robEntries).W)
}

class Wakeup(p: CoreParams = CoreParams()) extends Bundle {
  val valid = Bool()
  val phys = UInt(log2Ceil(p.physRegs).W)
  val data = UInt(p.xlen.W)
}

class MemRequest(p: CoreParams = CoreParams()) extends Bundle {
  val addr = UInt(p.xlen.W)
  val data = UInt(p.xlen.W)
  val isStore = Bool()
  val isSigned = Bool()
  val isAmo = Bool()
  val amoOp = UInt(5.W)
  val size = UInt(3.W)
}

class CsrCommand(p: CoreParams = CoreParams()) extends Bundle {
  val valid = Bool()
  val addr = UInt(12.W)
  val cmd = UInt(3.W)
  val rs1 = UInt(p.xlen.W)
  val zimm = UInt(5.W)
}

class TlbReq(p: CoreParams = CoreParams()) extends Bundle {
  val valid = Bool()
  val vaddr = UInt(p.xlen.W)
  val isStore = Bool()
  val isFetch = Bool()
}

class TlbResp(p: CoreParams = CoreParams()) extends Bundle {
  val hit = Bool()
  val miss = Bool()
  val paddr = UInt(p.xlen.W)
  val pageFault = Bool()
  val accessFault = Bool()
}

class TlbRefill(p: CoreParams = CoreParams()) extends Bundle {
  val valid = Bool()
  val vpn = UInt(27.W)
  val ppn = UInt(44.W)
  val level = UInt(2.W)
  val flags = UInt(8.W)
}

class PtwMemReq(p: CoreParams = CoreParams()) extends Bundle {
  val valid = Bool()
  val addr = UInt(p.xlen.W)
}

class PtwMemResp(p: CoreParams = CoreParams()) extends Bundle {
  val valid = Bool()
  val data = UInt(p.xlen.W)
}

class LoadQueueEntry(p: CoreParams = CoreParams()) extends Bundle {
  val valid = Bool()
  val robIdx = UInt(log2Ceil(p.robEntries).W)
  val addrValid = Bool()
  val addr = UInt(p.xlen.W)
  val size = UInt(3.W)
  val completed = Bool()
  val violation = Bool()
}

class StoreQueueEntry(p: CoreParams = CoreParams()) extends Bundle {
  val valid = Bool()
  val robIdx = UInt(log2Ceil(p.robEntries).W)
  val addrValid = Bool()
  val dataValid = Bool()
  val addr = UInt(p.xlen.W)
  val data = UInt(p.xlen.W)
  val size = UInt(3.W)
  val committed = Bool()
}