abnerhexu a32db39c80 fix: pass remaining riscv isa tests

2026-06-27 07:07:07 +00:00

generated-ooo

fix: pass remaining riscv isa tests

2026-06-27 07:07:07 +00:00

project

Initial Chisel core implementation

2026-06-26 08:20:25 +00:00

sim

fix: pass remaining riscv isa tests

2026-06-27 07:07:07 +00:00

src/main/scala

fix: pass remaining riscv isa tests

2026-06-27 07:07:07 +00:00

.gitignore

Initial Chisel core implementation

2026-06-26 08:20:25 +00:00

.gitmodules

fix: resolve OoO simulation timeout

2026-06-27 03:38:34 +00:00

ARCHITECTURE.md

Initial Chisel core implementation

2026-06-26 08:20:25 +00:00

build.sbt

Initial Chisel core implementation

2026-06-26 08:20:25 +00:00

Description

No description provided

1.4 MiB

Languages

SystemVerilog 96.6%

Scala 3%

C++ 0.3%