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f57fa82028eb5b0b12667ec37d815cf3c8ede601
vortex/hw/rtl
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Blaise Tine f57fa82028 cache bank select optimization
2021-07-15 11:42:17 -07:00
..
afu
minor update
2021-07-13 05:25:44 -07:00
cache
cache bank select optimization
2021-07-15 11:42:17 -07:00
fp_cores
reset network refactoring
2021-07-15 11:34:55 -07:00
interfaces
dcache response bus optimization
2021-07-12 10:14:48 -07:00
libs
reset network refactoring
2021-07-15 11:34:55 -07:00
.DS_Store
project directories reorganization
2020-04-14 06:35:20 -04:00
.gitignore
fix opae build
2020-04-20 12:51:42 -07:00
Vortex.v
reset network refactoring
2021-07-15 11:34:55 -07:00
VX_alu_unit.v
using onehot multiplexer to reduce critical path
2021-07-08 00:26:59 -07:00
VX_cluster.v
reset network refactoring
2021-07-15 11:34:55 -07:00
VX_commit.v
moving MUL unit into ALU unit
2021-02-23 13:49:02 -08:00
VX_config.vh
minor update
2021-06-22 09:30:36 -07:00
VX_core.v
dcache response bus optimization
2021-07-12 10:14:48 -07:00
VX_csr_data.v
decode optimization
2021-06-28 05:06:30 -07:00
VX_csr_unit.v
decode optimization
2021-06-28 05:06:30 -07:00
VX_decode.v
minor update
2021-07-08 01:31:12 -07:00
VX_define.vh
minor udpate
2021-06-28 09:14:06 -07:00
VX_execute.v
reset network refactoring
2021-07-15 11:34:55 -07:00
VX_fetch.v
cache request interfaces update
2021-02-10 20:55:04 -08:00
VX_fpu_unit.v
using onehot multiplexer to reduce critical path
2021-07-08 00:26:59 -07:00
VX_gpr_ram_f.v
minor update
2021-01-01 20:24:18 -08:00
VX_gpr_ram_i.v
fixed register file initialization to zero synthesis inference
2020-12-10 00:27:56 -08:00
VX_gpr_stage.v
Merge branch 'master' of https://github.gatech.edu/casl/Vortex
2021-03-04 20:51:03 -08:00
VX_gpu_unit.v
Merge branch 'master' of https://github.gatech.edu/casl/Vortex
2021-03-04 20:51:03 -08:00
VX_ibuffer.v
minor update
2021-07-03 04:47:19 -07:00
VX_icache_stage.v
Merge branch 'master' of https://github.gatech.edu/casl/Vortex
2021-03-04 20:51:03 -08:00
VX_instr_demux.v
adding data fence support
2021-06-28 06:12:18 -07:00
VX_ipdom_stack.v
critical path optimization - fpga fmax @4c = ~212 mhz
2020-12-26 03:28:32 -08:00
VX_issue.v
instr_sched => ibuffer
2021-06-27 19:36:43 -07:00
VX_lsu_unit.v
dcache response bus optimization
2021-07-12 10:14:48 -07:00
VX_mem_arb.v
non-cacheable memory address critical paths optimizations
2021-06-10 12:47:18 -07:00
VX_mem_unit.v
reset network refactoring
2021-07-15 11:34:55 -07:00
VX_muldiv.v
decode optimization
2021-06-28 05:06:30 -07:00
VX_pipeline.v
reset network refactoring
2021-07-15 11:34:55 -07:00
VX_platform.vh
reset network refactoring
2021-07-15 11:34:55 -07:00
VX_print_instr.vh
decode optimization
2021-06-28 05:06:30 -07:00
VX_scope.vh
moving MUL unit into ALU unit
2021-02-23 13:49:02 -08:00
VX_scoreboard.v
instr_sched => ibuffer
2021-06-27 19:36:43 -07:00
VX_smem_arb.v
dcache response bus optimization
2021-07-12 10:14:48 -07:00
VX_types.vh
FPU float<->int conversion optimization
2020-12-29 15:37:45 -08:00
VX_warp_sched.v
fix split/join hardware
2021-06-15 16:06:54 -04:00
VX_writeback.v
relaxing commit back-pressure in writeback stage
2021-03-15 14:39:55 -07:00