1903 lines
68 KiB
C++
1903 lines
68 KiB
C++
#include <iostream>
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#include <stdlib.h>
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#include <unistd.h>
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#include <math.h>
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#include <bitset>
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#include <climits>
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#include <sys/types.h>
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#include <sys/stat.h>
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#include <assert.h>
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#include <util.h>
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#include <rvfloats.h>
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#include "warp.h"
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#include "instr.h"
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#include "core.h"
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using namespace vortex;
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static bool HasDivergentThreads(const ThreadMask &thread_mask,
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const std::vector<std::vector<DoubleWord>> ®_file,
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unsigned reg) {
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bool cond;
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size_t thread_idx = 0;
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size_t num_threads = reg_file.size();
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for (; thread_idx < num_threads; ++thread_idx) {
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if (thread_mask[thread_idx]) {
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cond = bool(reg_file[thread_idx][reg]);
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break;
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}
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}
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assert(thread_idx != num_threads);
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for (; thread_idx < num_threads; ++thread_idx) {
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if (thread_mask[thread_idx]) {
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if (cond != (bool(reg_file[thread_idx][reg]))) {
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return true;
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}
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}
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}
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return false;
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}
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inline uint32_t get_fpu_rm(uint32_t func3, Core* core, uint32_t tid, uint32_t wid) {
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return (func3 == 0x7) ? core->get_csr(CSR_FRM, tid, wid) : func3;
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}
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inline void update_fcrs(uint32_t fflags, Core* core, uint32_t tid, uint32_t wid) {
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if (fflags) {
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core->set_csr(CSR_FCSR, core->get_csr(CSR_FCSR, tid, wid) | fflags, tid, wid);
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core->set_csr(CSR_FFLAGS, core->get_csr(CSR_FFLAGS, tid, wid) | fflags, tid, wid);
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}
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}
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void Warp::execute(const Instr &instr, Pipeline *pipeline) {
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assert(tmask_.any());
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// simx64
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DoubleWord nextPC = PC_ + 4;
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bool runOnce = false;
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Word func3 = instr.getFunc3();
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Word func6 = instr.getFunc6();
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Word func7 = instr.getFunc7();
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Word func2 = instr.getFunc2();
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auto opcode = instr.getOpcode();
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int rdest = instr.getRDest();
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int rsrc0 = instr.getRSrc(0);
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int rsrc1 = instr.getRSrc(1);
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DoubleWord immsrc= instr.getImm();
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DoubleWord vmask = instr.getVmask();
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int num_threads = core_->arch().num_threads();
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for (int t = 0; t < num_threads; t++) {
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if (!tmask_.test(t) || runOnce)
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continue;
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auto &iregs = iRegFile_.at(t);
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auto &fregs = fRegFile_.at(t);
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DoubleWord rsdata[3];
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DoubleWord rddata;
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int num_rsrcs = instr.getNRSrc();
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if (num_rsrcs) {
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DPH(2, "[" << std::dec << t << "] Src Regs: ");
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for (int i = 0; i < num_rsrcs; ++i) {
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int rst = instr.getRSType(i);
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int rs = instr.getRSrc(i);
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if (i) DPN(2, ", ");
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switch (rst) {
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case 1:
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rsdata[i] = iregs[rs];
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DPN(2, "r" << std::dec << rs << "=0x" << std::hex << rsdata[i]);
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break;
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case 2:
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rsdata[i] = fregs[rs];
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DPN(2, "fr" << std::dec << rs << "=0x" << std::hex << rsdata[i]);
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break;
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default: break;
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}
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}
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DPN(2, std::endl);
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}
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bool rd_write = false;
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switch (opcode) {
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case NOP:
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break;
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case LUI_INST:
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rddata = (immsrc << 12) & 0xfffffffffffff000;
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rd_write = true;
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break;
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case AUIPC_INST:
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// simx64
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rddata = ((immsrc << 12) & 0xfffffffffffff000) + PC_;
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rd_write = true;
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break;
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case R_INST: {
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if (func7 & 0x1) {
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switch (func3) {
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case 0:
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// RV32M: MUL
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rddata = ((DoubleWordI)rsdata[0]) * ((DoubleWordI)rsdata[1]);
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break;
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case 1: {
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// RV32M: MULH
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__int128_t first = signExt128((__int128_t)rsdata[0], 64, 0xFFFFFFFFFFFFFFFF);
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__int128_t second = signExt128((__int128_t)rsdata[1], 64, 0xFFFFFFFFFFFFFFFF);
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__uint128_t result = first * second;
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rddata = (result >> 64) & 0xFFFFFFFFFFFFFFFF;
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} break;
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case 2: {
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// RV32M: MULHSU
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__int128_t first = signExt128((__int128_t)rsdata[0], 64, 0xFFFFFFFFFFFFFFFF);
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__int128_t second = (__int128_t)rsdata[1];
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__uint128_t result = first * second;
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rddata = (result >> 64) & 0xFFFFFFFFFFFFFFFF;
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} break;
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case 3: {
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// RV32M: MULHU
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__uint128_t first = (__uint128_t)rsdata[0];
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__uint128_t second = (__uint128_t)rsdata[1];
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rddata = ((first * second) >> 64) & 0xFFFFFFFFFFFFFFFF;
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} break;
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case 4: {
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// RV32M: DIV
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DoubleWordI dividen = rsdata[0];
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DoubleWordI divisor = rsdata[1];
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if (divisor == 0) {
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rddata = -1;
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} else if (dividen == DoubleWordI(0x8000000000000000) && divisor == DoubleWordI(0xFFFFFFFFFFFFFFFF)) {
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rddata = dividen;
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} else {
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rddata = dividen / divisor;
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}
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} break;
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case 5: {
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// RV32M: DIVU
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DoubleWord dividen = rsdata[0];
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DoubleWord divisor = rsdata[1];
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if (divisor == 0) {
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rddata = -1;
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} else {
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rddata = dividen / divisor;
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}
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} break;
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case 6: {
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// RV32M: REM
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DoubleWordI dividen = rsdata[0];
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DoubleWordI divisor = rsdata[1];
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if (divisor == 0) {
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rddata = dividen;
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} else if (dividen == DoubleWordI(0x8000000000000000) && divisor == DoubleWordI(0xFFFFFFFFFFFFFFFF)) {
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rddata = 0;
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} else {
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rddata = dividen % divisor;
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}
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} break;
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case 7: {
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// RV32M: REMU
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DoubleWord dividen = rsdata[0];
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DoubleWord divisor = rsdata[1];
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if (divisor == 0) {
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rddata = dividen;
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} else {
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rddata = dividen % divisor;
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}
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} break;
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default:
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std::cout << "unsupported MUL/DIV instr\n";
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std::abort();
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}
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} else {
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switch (func3) {
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case 0:
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if (func7) {
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// RV32I: SUB
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rddata = rsdata[0] - rsdata[1];
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} else {
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// RV32I: ADD
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rddata = rsdata[0] + rsdata[1];
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}
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break;
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case 1:
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// RV32I: SLL
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rddata = rsdata[0] << rsdata[1];
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break;
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case 2:
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// RV32I: SLT (signed)
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rddata = (DoubleWordI(rsdata[0]) < DoubleWordI(rsdata[1]));
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break;
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case 3:
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// RV32I: SLTU (unsigned)
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rddata = (DoubleWord(rsdata[0]) < DoubleWord(rsdata[1]));
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break;
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case 4:
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// RV32I: XOR
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rddata = rsdata[0] ^ rsdata[1];
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break;
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case 5:
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if (func7) {
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// RV32I: SRA
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rddata = DoubleWordI(rsdata[0]) >> DoubleWordI(rsdata[1]);
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} else {
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// RV32I: SRL
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rddata = DoubleWord(rsdata[0]) >> DoubleWord(rsdata[1]);
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}
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break;
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case 6:
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// RV32I: OR
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rddata = rsdata[0] | rsdata[1];
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break;
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case 7:
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// RV32I: AND
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rddata = rsdata[0] & rsdata[1];
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break;
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default:
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std::abort();
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}
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}
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rd_write = true;
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} break;
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case I_INST:
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switch (func3) {
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case 0:
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// RV32I: ADDI
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rddata = rsdata[0] + immsrc;
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break;
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case 1:
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// RV64I: SLLI
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rddata = rsdata[0] << immsrc;
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break;
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case 2:
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// RV32I: SLTI
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rddata = (DoubleWordI(rsdata[0]) < DoubleWordI(immsrc));
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break;
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case 3: {
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// RV32I: SLTIU
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rddata = (DoubleWord(rsdata[0]) < DoubleWord(immsrc));
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} break;
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case 4:
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// RV32I: XORI
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rddata = rsdata[0] ^ immsrc;
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break;
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case 5:
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if (func7) {
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// RV64I: SRAI
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// rs1 shifted by lower 6 bits of immsrc
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DoubleWord result = DoubleWordI(rsdata[0]) >> immsrc;
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rddata = result;
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} else {
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// RV64I: SRLI
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// rs1 shifted by lower 6 bits of immsrc
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DoubleWord result = DoubleWord(rsdata[0]) >> immsrc;
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rddata = result;
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}
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break;
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case 6:
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// RV32I: ORI
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rddata = rsdata[0] | immsrc;
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break;
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case 7:
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// RV32I: ANDI
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rddata = rsdata[0] & immsrc;
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break;
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default:
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std::abort();
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}
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rd_write = true;
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break;
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case B_INST:
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switch (func3) {
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case 0:
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// RV32I: BEQ
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if (rsdata[0] == rsdata[1]) {
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nextPC = PC_ + immsrc;
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}
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break;
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case 1:
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// RV32I: BNE
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if (rsdata[0] != rsdata[1]) {
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nextPC = PC_ + immsrc;
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}
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break;
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case 4:
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// RV32I: BLT
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if (DoubleWordI(rsdata[0]) < DoubleWordI(rsdata[1])) {
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nextPC = PC_ + immsrc;
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}
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break;
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case 5:
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// RV32I: BGE
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if (DoubleWordI(rsdata[0]) >= DoubleWordI(rsdata[1])) {
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nextPC = PC_ + immsrc;
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}
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break;
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case 6:
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// RV32I: BLTU
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if (DoubleWord(rsdata[0]) < DoubleWord(rsdata[1])) {
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nextPC = PC_ + immsrc;
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}
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break;
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case 7:
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// RV32I: BGEU
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if (DoubleWord(rsdata[0]) >= DoubleWord(rsdata[1])) {
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nextPC = PC_ + immsrc;
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}
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break;
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}
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pipeline->stall_warp = true;
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runOnce = true;
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break;
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// RV32I: JAL
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case JAL_INST:
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rddata = nextPC;
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nextPC = PC_ + immsrc;
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pipeline->stall_warp = true;
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runOnce = true;
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rd_write = true;
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break;
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// RV32I: JALR
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case JALR_INST:
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rddata = nextPC;
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nextPC = DoubleWord(rsdata[0]) + DoubleWord(immsrc);
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pipeline->stall_warp = true;
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runOnce = true;
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rd_write = true;
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break;
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case L_INST: {
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DoubleWord memAddr = ((rsdata[0] + immsrc) & 0xFFFFFFF8); // DoubleWord aligned
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DoubleWord shift_by = ((rsdata[0] + immsrc) & 0x00000007) * 8;
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DoubleWord data_read = core_->dcache_read(memAddr, 8);
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D(3, "LOAD MEM: ADDRESS=0x" << std::hex << memAddr << ", DATA=0x" << data_read);
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switch (func3) {
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case 0:
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// RV32I: LBI
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rddata = signExt((data_read >> shift_by) & 0xFF, 8, 0xFF);
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break;
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case 1:
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// RV32I: LHI
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rddata = signExt((data_read >> shift_by) & 0xFFFF, 16, 0xFFFF);
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break;
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case 2:
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// RV32I: LW
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rddata = signExt((data_read >> shift_by) & 0xFFFFFFFF, 32, 0xFFFFFFFF);
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break;
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case 3:
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// RV64I: LD
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rddata = DoubleWord(data_read);
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break;
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case 4:
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// RV32I: LBU
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rddata = DoubleWord((data_read >> shift_by) & 0xFF);
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break;
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case 5:
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// RV32I: LHU
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rddata = DoubleWord((data_read >> shift_by) & 0xFFFF);
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break;
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case 6:
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// RV64I: LWU
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rddata = DoubleWord((data_read >> shift_by) & 0xFFFFFFFF);
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break;
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default:
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std::abort();
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}
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rd_write = true;
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} break;
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case S_INST: {
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DoubleWord memAddr = rsdata[0] + immsrc;
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D(3, "STORE MEM: ADDRESS=0x" << std::hex << memAddr);
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switch (func3) {
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case 0:
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// RV32I: SB
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core_->dcache_write(memAddr, rsdata[1] & 0x000000FF, 1);
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break;
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case 1:
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// RV32I: SH
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core_->dcache_write(memAddr, rsdata[1] & 0x0000FFFF, 2);
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break;
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case 2:
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// RV32I: SW
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core_->dcache_write(memAddr, rsdata[1] & 0xFFFFFFFF, 4);
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break;
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case 3:
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// RV64I: SD
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core_ ->dcache_write(memAddr, rsdata[1], 8);
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break;
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default:
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std::abort();
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}
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} break;
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// simx64
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case R_INST_64: {
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if (func7 & 0x1){
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switch (func3) {
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case 0:
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// RV64M: MULW
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rddata = signExt((WordI)rsdata[0] * (WordI)rsdata[1], 32, 0xFFFFFFFF);
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break;
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case 4: {
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// RV64M: DIVW
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int32_t dividen = (WordI) rsdata[0];
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int32_t divisor = (WordI) rsdata[1];
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if (divisor == 0){
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rddata = -1;
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} else if (dividen == WordI(0x80000000) && divisor == WordI(0xFFFFFFFF)) {
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rddata = signExt(dividen, 32, 0xFFFFFFFF);
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} else {
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rddata = signExt(dividen / divisor, 32, 0xFFFFFFFF);
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}
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} break;
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case 5: {
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// RV64M: DIVUW
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uint32_t dividen = (Word) rsdata[0];
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uint32_t divisor = (Word) rsdata[1];
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if (divisor == 0){
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rddata = -1;
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} else {
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rddata = signExt(dividen / divisor, 32, 0xFFFFFFFF);
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}
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} break;
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case 6: {
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// RV64M: REMW
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int32_t dividen = (WordI) rsdata[0];
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int32_t divisor = (WordI) rsdata[1];
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if (divisor == 0){
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rddata = signExt(dividen, 32, 0xFFFFFFFF);
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} else if (dividen == WordI(0x80000000) && divisor == WordI(0xFFFFFFFF)) {
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rddata = 0;
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} else {
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rddata = signExt(dividen % divisor, 32, 0xFFFFFFFF);
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}
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} break;
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case 7: {
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// RV64M: REMUW
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uint32_t dividen = (Word) rsdata[0];
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uint32_t divisor = (Word) rsdata[1];
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if (divisor == 0){
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rddata = signExt(dividen, 32, 0xFFFFFFFF);
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} else {
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rddata = signExt(dividen % divisor, 32, 0xFFFFFFFF);
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}
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} break;
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default:
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std::abort();
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}
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} else {
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switch (func3) {
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case 0:
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if (func7){
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// RV64I: SUBW
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rddata = signExt((Word)rsdata[0] - (Word)rsdata[1], 32, 0xFFFFFFFF);
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}
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else{
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// RV64I: ADDW
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rddata = signExt((Word)rsdata[0] + (Word)rsdata[1], 32, 0xFFFFFFFF);
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}
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break;
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case 1:
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// RV64I: SLLW
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rddata = signExt((Word)rsdata[0] << (Word)rsdata[1], 32, 0xFFFFFFFF);
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break;
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case 5:
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if (func7) {
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// RV64I: SRAW
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rddata = signExt((WordI)rsdata[0] >> (WordI)rsdata[1], 32, 0xFFFFFFFF);
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} else {
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// RV64I: SRLW
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rddata = signExt((Word)rsdata[0] >> (Word)rsdata[1], 32, 0xFFFFFFFF);
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}
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break;
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default:
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std::abort();
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}
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}
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rd_write = true;
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} break;
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|
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// simx64
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case I_INST_64: {
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switch (func3) {
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case 0:
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// RV64I: ADDIW
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rddata = signExt((Word)rsdata[0] + (Word)immsrc, 32, 0xFFFFFFFF);
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break;
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case 1:
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// RV64I: SLLIW
|
|
rddata = signExt((Word)rsdata[0] << (Word)immsrc, 32, 0xFFFFFFFF);
|
|
break;
|
|
case 5:
|
|
if (func7) {
|
|
// RV64I: SRAIW
|
|
DoubleWord result = signExt((WordI)rsdata[0] >> (WordI)immsrc, 32, 0xFFFFFFFF);
|
|
rddata = result;
|
|
} else {
|
|
// RV64I: SRLIW
|
|
DoubleWord result = signExt((Word)rsdata[0] >> (Word)immsrc, 32, 0xFFFFFFFF);
|
|
rddata = result;
|
|
}
|
|
break;
|
|
default:
|
|
std::abort();
|
|
}
|
|
rd_write = true;
|
|
} break;
|
|
case SYS_INST: {
|
|
DoubleWord csr_addr = immsrc & 0x00000FFF;
|
|
DoubleWord csr_value = core_->get_csr(csr_addr, t, id_);
|
|
switch (func3) {
|
|
case 0:
|
|
if (csr_addr < 2) {
|
|
// ECALL/EBREAK
|
|
core_->trigger_ebreak();
|
|
}
|
|
break;
|
|
case 1:
|
|
// RV32I: CSRRW
|
|
rddata = csr_value;
|
|
core_->set_csr(csr_addr, rsdata[0], t, id_);
|
|
rd_write = true;
|
|
break;
|
|
case 2:
|
|
// RV32I: CSRRS
|
|
rddata = csr_value;
|
|
core_->set_csr(csr_addr, csr_value | rsdata[0], t, id_);
|
|
rd_write = true;
|
|
break;
|
|
case 3:
|
|
// RV32I: CSRRC
|
|
rddata = csr_value;
|
|
core_->set_csr(csr_addr, csr_value & ~rsdata[0], t, id_);
|
|
rd_write = true;
|
|
break;
|
|
case 5:
|
|
// RV32I: CSRRWI
|
|
rddata = csr_value;
|
|
core_->set_csr(csr_addr, rsrc0, t, id_);
|
|
rd_write = true;
|
|
break;
|
|
case 6:
|
|
// RV32I: CSRRSI
|
|
rddata = csr_value;
|
|
core_->set_csr(csr_addr, csr_value | rsrc0, t, id_);
|
|
rd_write = true;
|
|
break;
|
|
case 7:
|
|
// RV32I: CSRRCI
|
|
rddata = csr_value;
|
|
core_->set_csr(csr_addr, csr_value & ~rsrc0, t, id_);
|
|
rd_write = true;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
} break;
|
|
// RV32I: FENCE
|
|
case FENCE:
|
|
pipeline->stall_warp = true;
|
|
runOnce = true;
|
|
break;
|
|
case (FL | VL):
|
|
if (func3 == 0x2) {
|
|
// RV32F: FLW
|
|
DoubleWord memAddr = rsdata[0] + immsrc;
|
|
DoubleWord data_read = core_->dcache_read(memAddr, 4);
|
|
D(3, "LOAD MEM: ADDRESS=0x" << std::hex << memAddr << ", DATA=0x" << data_read);
|
|
rddata = data_read | 0xFFFFFFFF00000000;
|
|
} else if (func3 == 0x3) {
|
|
// RV32D: FLD
|
|
DoubleWord memAddr = ((rsdata[0] + immsrc) & 0xFFFFFFF8);
|
|
DoubleWord data_read = core_->dcache_read(memAddr, 8);
|
|
D(3, "LOAD MEM: ADDRESS=0x" << std::hex << memAddr << ", DATA=0x" << data_read);
|
|
rddata = data_read;
|
|
} else {
|
|
D(3, "Executing vector load");
|
|
D(3, "lmul: " << vtype_.vlmul << " VLEN:" << (core_->arch().vsize() * 8) << "sew: " << vtype_.vsew);
|
|
D(3, "src: " << rsrc0 << " " << rsdata[0]);
|
|
D(3, "dest" << rdest);
|
|
D(3, "width" << instr.getVlsWidth());
|
|
|
|
auto &vd = vRegFile_[rdest];
|
|
|
|
switch (instr.getVlsWidth()) {
|
|
case 6: {
|
|
//load DoubleWord and unit strided (not checking for unit stride)
|
|
for (int i = 0; i < vl_; i++) {
|
|
DoubleWord memAddr = ((rsdata[0]) & 0xFFFFFFFC) + (i * vtype_.vsew / 8);
|
|
D(3, "STORE MEM: ADDRESS=0x" << std::hex << memAddr);
|
|
DoubleWord data_read = core_->dcache_read(memAddr, 4);
|
|
D(3, "Mem addr: " << std::hex << memAddr << " Data read " << data_read);
|
|
int *result_ptr = (int *)(vd.data() + i);
|
|
*result_ptr = data_read;
|
|
}
|
|
} break;
|
|
default:
|
|
std::abort();
|
|
}
|
|
break;
|
|
}
|
|
rd_write = true;
|
|
break;
|
|
case (FS | VS):
|
|
if (func3 == 0x2) {
|
|
// RV32F: FSW
|
|
DoubleWord memAddr = rsdata[0] + immsrc;
|
|
core_->dcache_write(memAddr, rsdata[1], 4);
|
|
D(3, "STORE MEM: ADDRESS=0x" << std::hex << memAddr);
|
|
} else if (func3 == 0x3){
|
|
// RV32D: FSD
|
|
DoubleWord memAddr = rsdata[0] + immsrc;
|
|
core_->dcache_write(memAddr, rsdata[1], 8);
|
|
D(3, "STORE MEM: ADDRESS=0x" << std::hex << memAddr);
|
|
} else {
|
|
for (int i = 0; i < vl_; i++) {
|
|
DoubleWord memAddr = rsdata[0] + (i * vtype_.vsew / 8);
|
|
D(3, "STORE MEM: ADDRESS=0x" << std::hex << memAddr);
|
|
switch (instr.getVlsWidth()) {
|
|
case 6: {
|
|
//store DoubleWord and unit strided (not checking for unit stride)
|
|
uint32_t value = *(uint32_t *)(vRegFile_[instr.getVs3()].data() + i);
|
|
core_->dcache_write(memAddr, value, 4);
|
|
D(3, "store: " << memAddr << " value:" << value);
|
|
} break;
|
|
default:
|
|
std::abort();
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
case FCI: {
|
|
uint32_t frm = get_fpu_rm(func3, core_, t, id_);
|
|
uint32_t fflags = 0;
|
|
switch (func7) {
|
|
case 0x00: // RV32F: FADD.S
|
|
rddata = rv_fadd(rsdata[0], rsdata[1], frm, &fflags);
|
|
break;
|
|
case 0x01: // RV32D: FADD.D
|
|
rddata = rv_fadd_d(rsdata[0], rsdata[1], frm, &fflags);
|
|
break;
|
|
case 0x04: // RV32F: FSUB.S
|
|
rddata = rv_fsub(rsdata[0], rsdata[1], frm, &fflags);
|
|
break;
|
|
case 0x05: // RV32D: FSUB.D
|
|
rddata = rv_fsub_d(rsdata[0], rsdata[1], frm, &fflags);
|
|
break;
|
|
case 0x08: // RV32F: FMUL.S
|
|
rddata = rv_fmul(rsdata[0], rsdata[1], frm, &fflags);
|
|
break;
|
|
case 0x09: // RV32D: FMUL.D
|
|
rddata = rv_fmul_d(rsdata[0], rsdata[1], frm, &fflags);
|
|
break;
|
|
case 0x0c: // RV32F: FDIV.S
|
|
rddata = rv_fdiv(rsdata[0], rsdata[1], frm, &fflags);
|
|
break;
|
|
case 0x0d: // RV32D: FDIV.D
|
|
rddata = rv_fdiv_d(rsdata[0], rsdata[1], frm, &fflags);
|
|
break;
|
|
case 0x2c: // RV32F: FSQRT.S
|
|
rddata = rv_fsqrt(rsdata[0], frm, &fflags);
|
|
break;
|
|
case 0x2d: // RV32D: FSQRT.D
|
|
rddata = rv_fsqrt_d(rsdata[0], frm, &fflags);
|
|
break;
|
|
case 0x10:
|
|
switch (func3) {
|
|
case 0: // RV32F: FSGNJ.S
|
|
rddata = rv_fsgnj((Word)rsdata[0], (Word)rsdata[1]) | 0xFFFFFFFF00000000;
|
|
break;
|
|
case 1: // RV32F: FSGNJN.S
|
|
rddata = rv_fsgnjn((Word)rsdata[0], (Word)rsdata[1]) | 0xFFFFFFFF00000000;
|
|
break;
|
|
case 2: // RV32F: FSGNJX.S
|
|
rddata = rv_fsgnjx((Word)rsdata[0], (Word)rsdata[1]) | 0xFFFFFFFF00000000;
|
|
break;
|
|
}
|
|
break;
|
|
case 0x11:
|
|
switch (func3) {
|
|
case 0: // RV32D: FSGNJ.D
|
|
rddata = rv_fsgnj_d(rsdata[0], rsdata[1]);
|
|
break;
|
|
case 1: // RV32D: FSGNJN.D
|
|
rddata = rv_fsgnjn_d(rsdata[0], rsdata[1]);
|
|
break;
|
|
case 2: // RV32D: FSGNJX.D
|
|
rddata = rv_fsgnjx_d(rsdata[0], rsdata[1]);
|
|
break;
|
|
}
|
|
break;
|
|
case 0x14:
|
|
if (func3) {
|
|
// RV32F: FMAX.S
|
|
rddata = rv_fmax(rsdata[0], rsdata[1], &fflags);
|
|
} else {
|
|
// RV32F: FMIN.S
|
|
rddata = rv_fmin(rsdata[0], rsdata[1], &fflags);
|
|
}
|
|
break;
|
|
case 0x15:
|
|
if (func3) {
|
|
// RV32D: FMAX.D
|
|
rddata = rv_fmax_d(rsdata[0], rsdata[1], &fflags);
|
|
} else {
|
|
// RV32D: FMIN.D
|
|
rddata = rv_fmin_d(rsdata[0], rsdata[1], &fflags);
|
|
}
|
|
break;
|
|
case 0x20: rddata = rv_dtof(rsdata[0]);
|
|
break;
|
|
case 0x21: rddata = rv_ftod(rsdata[0]);
|
|
break;
|
|
case 0x60:
|
|
switch(rsrc1) {
|
|
case 0:
|
|
// RV32F: FCVT.W.S
|
|
rddata = signExt(rv_ftoi(rsdata[0], frm, &fflags), 32, 0xFFFFFFFF);
|
|
break;
|
|
case 1:
|
|
// RV32F: FCVT.WU.S
|
|
rddata = signExt(rv_ftou(rsdata[0], frm, &fflags), 32, 0xFFFFFFFF);
|
|
break;
|
|
case 2:
|
|
// RV64F: FCVT.L.S
|
|
rddata = rv_ftol(rsdata[0], frm, &fflags);
|
|
break;
|
|
case 3:
|
|
// RV64F: FCVT.LU.S
|
|
rddata = rv_ftolu(rsdata[0], frm, &fflags);
|
|
break;
|
|
}
|
|
break;
|
|
case 0x61:
|
|
switch(rsrc1) {
|
|
case 0:
|
|
// RV32D: FCVT.W.D
|
|
rddata = signExt(rv_ftoi_d(rsdata[0], frm, &fflags), 32, 0xFFFFFFFF);
|
|
break;
|
|
case 1:
|
|
// RV32D: FCVT.WU.D
|
|
rddata = signExt(rv_ftou_d(rsdata[0], frm, &fflags), 32, 0xFFFFFFFF);
|
|
break;
|
|
case 2:
|
|
// RV64D: FCVT.L.D
|
|
rddata = rv_ftol_d(rsdata[0], frm, &fflags);
|
|
break;
|
|
case 3:
|
|
// RV64D: FCVT.LU.D
|
|
rddata = rv_ftolu_d(rsdata[0], frm, &fflags);
|
|
break;
|
|
}
|
|
break;
|
|
case 0x70:
|
|
if (func3) {
|
|
// RV32F: FCLASS.S
|
|
rddata = rv_fclss(rsdata[0]);
|
|
} else {
|
|
// RV32F: FMV.X.W
|
|
rddata = signExt((Word)rsdata[0], 32, 0xFFFFFFFF);
|
|
}
|
|
break;
|
|
case 0x71:
|
|
if (func3) {
|
|
// RV32D: FCLASS.D
|
|
rddata = rv_fclss_d(rsdata[0]);
|
|
} else {
|
|
// RV64D: FMV.X.D
|
|
rddata = rsdata[0];
|
|
}
|
|
break;
|
|
case 0x50:
|
|
switch(func3) {
|
|
case 0:
|
|
// RV32F: FLE.S
|
|
rddata = rv_fle(rsdata[0], rsdata[1], &fflags);
|
|
break;
|
|
case 1:
|
|
// RV32F: FLT.S
|
|
rddata = rv_flt(rsdata[0], rsdata[1], &fflags);
|
|
break;
|
|
case 2:
|
|
// RV32F: FEQ.S
|
|
rddata = rv_feq(rsdata[0], rsdata[1], &fflags);
|
|
break;
|
|
} break;
|
|
case 0x51:
|
|
switch(func3) {
|
|
case 0:
|
|
// RV32D: FLE.D
|
|
rddata = rv_fle_d(rsdata[0], rsdata[1], &fflags);
|
|
break;
|
|
case 1:
|
|
// RV32D: FLT.D
|
|
rddata = rv_flt_d(rsdata[0], rsdata[1], &fflags);
|
|
break;
|
|
case 2:
|
|
// RV32D: FEQ.D
|
|
rddata = rv_feq_d(rsdata[0], rsdata[1], &fflags);
|
|
break;
|
|
} break;
|
|
case 0x68:
|
|
switch(rsrc1) {
|
|
case 0:
|
|
// RV32F: FCVT.S.W
|
|
rddata = rv_itof(rsdata[0], frm, &fflags);
|
|
break;
|
|
case 1:
|
|
// RV32F: FCVT.S.WU
|
|
rddata = rv_utof(rsdata[0], frm, &fflags);
|
|
break;
|
|
case 2:
|
|
// RV64F: FCVT.S.L
|
|
rddata = rv_ltof(rsdata[0], frm, &fflags);
|
|
break;
|
|
case 3:
|
|
// RV64F: FCVT.S.LU
|
|
rddata = rv_lutof(rsdata[0], frm, &fflags);
|
|
break;
|
|
}
|
|
break;
|
|
case 0x69:
|
|
switch(rsrc1) {
|
|
case 0:
|
|
// RV32D: FCVT.D.W
|
|
rddata = rv_itof_d(rsdata[0], frm, &fflags);
|
|
break;
|
|
case 1:
|
|
// RV32F: FCVT.D.WU
|
|
rddata = rv_utof_d(rsdata[0], frm, &fflags);
|
|
break;
|
|
case 2:
|
|
// RV64D: FCVT.D.L
|
|
rddata = rv_ltof_d(rsdata[0], frm, &fflags);
|
|
break;
|
|
case 3:
|
|
// RV64D: FCVT.D.LU
|
|
rddata = rv_lutof_d(rsdata[0], frm, &fflags);
|
|
break;
|
|
}
|
|
break;
|
|
case 0x78:
|
|
// RV32F: FMV.W.X
|
|
rddata = rsdata[0];
|
|
break;
|
|
case 0x79:
|
|
// RV64D: FMV.D.X
|
|
rddata = rsdata[0];
|
|
break;
|
|
}
|
|
update_fcrs(fflags, core_, t, id_);
|
|
rd_write = true;
|
|
} break;
|
|
case FMADD:
|
|
case FMSUB:
|
|
case FMNMADD:
|
|
case FMNMSUB: {
|
|
int frm = get_fpu_rm(func3, core_, t, id_);
|
|
// simx64
|
|
Word fflags = 0;
|
|
switch (opcode) {
|
|
case FMADD:
|
|
if (func2)
|
|
// RV32D: FMADD.D
|
|
rddata = rv_fmadd_d(rsdata[0], rsdata[1], rsdata[2], frm, &fflags);
|
|
else
|
|
// RV32F: FMADD.S
|
|
rddata = rv_fmadd(rsdata[0], rsdata[1], rsdata[2], frm, &fflags);
|
|
break;
|
|
case FMSUB:
|
|
if (func2)
|
|
// RV32D: FMSUB.D
|
|
rddata = rv_fmsub_d(rsdata[0],rsdata[1], rsdata[2], frm, &fflags);
|
|
else
|
|
// RV32F: FMSUB.S
|
|
rddata = rv_fmsub(rsdata[0], rsdata[1], rsdata[2], frm, &fflags);
|
|
break;
|
|
case FMNMADD:
|
|
if (func2)
|
|
// RV32D: FNMADD.D
|
|
rddata = rv_fnmadd_d(rsdata[0], rsdata[1], rsdata[2], frm, &fflags);
|
|
else
|
|
// RV32F: FNMADD.S
|
|
rddata = rv_fnmadd(rsdata[0], rsdata[1], rsdata[2], frm, &fflags);
|
|
break;
|
|
case FMNMSUB:
|
|
if (func2)
|
|
// RV32D: FNMSUB.D
|
|
rddata = rv_fnmsub_d(rsdata[0], rsdata[1], rsdata[2], frm, &fflags);
|
|
else
|
|
// RV32F: FNMSUB.S
|
|
rddata = rv_fnmsub(rsdata[0], rsdata[1], rsdata[2], frm, &fflags);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
update_fcrs(fflags, core_, t, id_);
|
|
rd_write = true;
|
|
} break;
|
|
case GPGPU:
|
|
switch (func3) {
|
|
case 0: {
|
|
// TMC
|
|
if (rsrc1) {
|
|
// predicate mode
|
|
ThreadMask pred;
|
|
for (int i = 0; i < num_threads; ++i) {
|
|
pred[i] = tmask_[i] ? (iRegFile_[i][rsrc0] != 0) : 0;
|
|
}
|
|
if (pred.any()) {
|
|
tmask_ &= pred;
|
|
}
|
|
} else {
|
|
tmask_.reset();
|
|
for (int i = 0; i < num_threads; ++i) {
|
|
tmask_[i] = rsdata[0] & (1 << i);
|
|
}
|
|
}
|
|
D(3, "*** TMC " << tmask_);
|
|
active_ = tmask_.any();
|
|
pipeline->stall_warp = true;
|
|
runOnce = true;
|
|
} break;
|
|
case 1: {
|
|
// WSPAWN
|
|
int active_warps = std::min<int>(rsdata[0], core_->arch().num_warps());
|
|
D(3, "*** Spawning " << (active_warps-1) << " warps at PC: " << std::hex << rsdata[1]);
|
|
for (int i = 1; i < active_warps; ++i) {
|
|
Warp &newWarp = core_->warp(i);
|
|
newWarp.setPC(rsdata[1]);
|
|
newWarp.setTmask(0, true);
|
|
}
|
|
pipeline->stall_warp = true;
|
|
runOnce = true;
|
|
} break;
|
|
case 2: {
|
|
// SPLIT
|
|
if (HasDivergentThreads(tmask_, iRegFile_, rsrc0)) {
|
|
ThreadMask tmask;
|
|
for (int i = 0; i < num_threads; ++i) {
|
|
tmask[i] = tmask_[i] && !iRegFile_[i][rsrc0];
|
|
}
|
|
|
|
DomStackEntry e(tmask, nextPC);
|
|
domStack_.push(tmask_);
|
|
domStack_.push(e);
|
|
for (size_t i = 0; i < e.tmask.size(); ++i) {
|
|
tmask_[i] = !e.tmask[i] && tmask_[i];
|
|
}
|
|
active_ = tmask_.any();
|
|
|
|
DPH(3, "*** Split: New TM=");
|
|
for (int i = 0; i < num_threads; ++i) DPN(3, tmask_[num_threads-i-1]);
|
|
DPN(3, ", Pushed TM=");
|
|
for (int i = 0; i < num_threads; ++i) DPN(3, e.tmask[num_threads-i-1]);
|
|
DPN(3, ", PC=0x" << std::hex << e.PC << "\n");
|
|
} else {
|
|
D(3, "*** Unanimous pred");
|
|
DomStackEntry e(tmask_);
|
|
e.unanimous = true;
|
|
domStack_.push(e);
|
|
}
|
|
pipeline->stall_warp = true;
|
|
runOnce = true;
|
|
} break;
|
|
case 3: {
|
|
// JOIN
|
|
if (!domStack_.empty() && domStack_.top().unanimous) {
|
|
D(3, "*** Uninimous branch at join");
|
|
tmask_ = domStack_.top().tmask;
|
|
active_ = tmask_.any();
|
|
domStack_.pop();
|
|
} else {
|
|
if (!domStack_.top().fallThrough) {
|
|
nextPC = domStack_.top().PC;
|
|
D(3, "*** Join: next PC: " << std::hex << nextPC << std::dec);
|
|
}
|
|
|
|
tmask_ = domStack_.top().tmask;
|
|
active_ = tmask_.any();
|
|
|
|
DPH(3, "*** Join: New TM=");
|
|
for (int i = 0; i < num_threads; ++i) DPN(3, tmask_[num_threads-i-1]);
|
|
DPN(3, "\n");
|
|
|
|
domStack_.pop();
|
|
}
|
|
pipeline->stall_warp = true;
|
|
runOnce = true;
|
|
} break;
|
|
case 4: {
|
|
// BAR
|
|
active_ = false;
|
|
core_->barrier(rsdata[0], rsdata[1], id_);
|
|
pipeline->stall_warp = true;
|
|
runOnce = true;
|
|
} break;
|
|
case 6: {
|
|
// PREFETCH
|
|
int addr = rsdata[0];
|
|
printf("*** PREFETCHED %d ***\n", addr);
|
|
} break;
|
|
default:
|
|
std::abort();
|
|
}
|
|
break;
|
|
case VSET: {
|
|
int VLEN = core_->arch().vsize() * 8;
|
|
int VLMAX = (instr.getVlmul() * VLEN) / instr.getVsew();
|
|
switch (func3) {
|
|
case 0: // vector-vector
|
|
switch (func6) {
|
|
case 0: {
|
|
auto& vr1 = vRegFile_[rsrc0];
|
|
auto& vr2 = vRegFile_[rsrc1];
|
|
auto& vd = vRegFile_[rdest];
|
|
auto& mask = vRegFile_[0];
|
|
if (vtype_.vsew == 8) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
uint8_t emask = *(uint8_t *)(mask.data() + i);
|
|
uint8_t value = emask & 0x1;
|
|
if (vmask || (!vmask && value)) {
|
|
uint8_t first = *(uint8_t *)(vr1.data() + i);
|
|
uint8_t second = *(uint8_t *)(vr2.data() + i);
|
|
uint8_t result = first + second;
|
|
D(3, "Adding " << first << " + " << second << " = " << result);
|
|
*(uint8_t *)(vd.data() + i) = result;
|
|
}
|
|
}
|
|
} else if (vtype_.vsew == 16) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
uint16_t emask = *(uint16_t *)(mask.data() + i);
|
|
uint16_t value = emask & 0x1;
|
|
if (vmask || (!vmask && value)) {
|
|
uint16_t first = *(uint16_t *)(vr1.data() + i);
|
|
uint16_t second = *(uint16_t *)(vr2.data() + i);
|
|
uint16_t result = first + second;
|
|
D(3, "Adding " << first << " + " << second << " = " << result);
|
|
*(uint16_t *)(vd.data() + i) = result;
|
|
}
|
|
}
|
|
} else if (vtype_.vsew == 32) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
uint32_t emask = *(uint32_t *)(mask.data() + i);
|
|
uint32_t value = emask & 0x1;
|
|
if (vmask || (!vmask && value)) {
|
|
uint32_t first = *(uint32_t *)(vr1.data() + i);
|
|
uint32_t second = *(uint32_t *)(vr2.data() + i);
|
|
uint32_t result = first + second;
|
|
D(3, "Adding " << first << " + " << second << " = " << result);
|
|
*(uint32_t *)(vd.data() + i) = result;
|
|
}
|
|
}
|
|
}
|
|
} break;
|
|
case 24: {
|
|
//vmseq
|
|
auto &vr1 = vRegFile_[rsrc0];
|
|
auto &vr2 = vRegFile_[rsrc1];
|
|
auto &vd = vRegFile_[rdest];
|
|
if (vtype_.vsew == 8) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
uint8_t first = *(uint8_t *)(vr1.data() + i);
|
|
uint8_t second = *(uint8_t *)(vr2.data() + i);
|
|
uint8_t result = (first == second) ? 1 : 0;
|
|
D(3, "Comparing " << first << " + " << second << " = " << result);
|
|
*(uint8_t *)(vd.data() + i) = result;
|
|
}
|
|
} else if (vtype_.vsew == 16) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
uint16_t first = *(uint16_t *)(vr1.data() + i);
|
|
uint16_t second = *(uint16_t *)(vr2.data() + i);
|
|
uint16_t result = (first == second) ? 1 : 0;
|
|
D(3, "Comparing " << first << " + " << second << " = " << result);
|
|
*(uint16_t *)(vd.data() + i) = result;
|
|
}
|
|
} else if (vtype_.vsew == 32) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
uint32_t first = *(uint32_t *)(vr1.data() + i);
|
|
uint32_t second = *(uint32_t *)(vr2.data() + i);
|
|
uint32_t result = (first == second) ? 1 : 0;
|
|
D(3, "Comparing " << first << " + " << second << " = " << result);
|
|
*(uint32_t *)(vd.data() + i) = result;
|
|
}
|
|
}
|
|
} break;
|
|
case 25: {
|
|
//vmsne
|
|
auto &vr1 = vRegFile_[rsrc0];
|
|
auto &vr2 = vRegFile_[rsrc1];
|
|
auto &vd = vRegFile_[rdest];
|
|
if (vtype_.vsew == 8) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
uint8_t first = *(uint8_t *)(vr1.data() + i);
|
|
uint8_t second = *(uint8_t *)(vr2.data() + i);
|
|
uint8_t result = (first != second) ? 1 : 0;
|
|
D(3, "Comparing " << first << " + " << second << " = " << result);
|
|
*(uint8_t *)(vd.data() + i) = result;
|
|
}
|
|
} else if (vtype_.vsew == 16) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
uint16_t first = *(uint16_t *)(vr1.data() + i);
|
|
uint16_t second = *(uint16_t *)(vr2.data() + i);
|
|
uint16_t result = (first != second) ? 1 : 0;
|
|
D(3, "Comparing " << first << " + " << second << " = " << result);
|
|
*(uint16_t *)(vd.data() + i) = result;
|
|
}
|
|
} else if (vtype_.vsew == 32) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
uint32_t first = *(uint32_t *)(vr1.data() + i);
|
|
uint32_t second = *(uint32_t *)(vr2.data() + i);
|
|
uint32_t result = (first != second) ? 1 : 0;
|
|
D(3, "Comparing " << first << " + " << second << " = " << result);
|
|
*(uint32_t *)(vd.data() + i) = result;
|
|
}
|
|
}
|
|
} break;
|
|
case 26: {
|
|
//vmsltu
|
|
auto &vr1 = vRegFile_[rsrc0];
|
|
auto &vr2 = vRegFile_[rsrc1];
|
|
auto &vd = vRegFile_[rdest];
|
|
if (vtype_.vsew == 8) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
uint8_t first = *(uint8_t *)(vr1.data() + i);
|
|
uint8_t second = *(uint8_t *)(vr2.data() + i);
|
|
uint8_t result = (first < second) ? 1 : 0;
|
|
D(3, "Comparing " << first << " + " << second << " = " << result);
|
|
*(uint8_t *)(vd.data() + i) = result;
|
|
}
|
|
} else if (vtype_.vsew == 16) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
uint16_t first = *(uint16_t *)(vr1.data() + i);
|
|
uint16_t second = *(uint16_t *)(vr2.data() + i);
|
|
uint16_t result = (first < second) ? 1 : 0;
|
|
D(3, "Comparing " << first << " + " << second << " = " << result);
|
|
*(uint16_t *)(vd.data() + i) = result;
|
|
}
|
|
} else if (vtype_.vsew == 32) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
uint32_t first = *(uint32_t *)(vr1.data() + i);
|
|
uint32_t second = *(uint32_t *)(vr2.data() + i);
|
|
uint32_t result = (first < second) ? 1 : 0;
|
|
D(3, "Comparing " << first << " + " << second << " = " << result);
|
|
*(uint32_t *)(vd.data() + i) = result;
|
|
}
|
|
}
|
|
} break;
|
|
case 27: {
|
|
//vmslt
|
|
auto &vr1 = vRegFile_[rsrc0];
|
|
auto &vr2 = vRegFile_[rsrc1];
|
|
auto &vd = vRegFile_[rdest];
|
|
if (vtype_.vsew == 8) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
int8_t first = *(int8_t *)(vr1.data() + i);
|
|
int8_t second = *(int8_t *)(vr2.data() + i);
|
|
int8_t result = (first < second) ? 1 : 0;
|
|
D(3, "Comparing " << first << " + " << second << " = " << result);
|
|
*(uint8_t *)(vd.data() + i) = result;
|
|
}
|
|
} else if (vtype_.vsew == 16) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
int16_t first = *(int16_t *)(vr1.data() + i);
|
|
int16_t second = *(int16_t *)(vr2.data() + i);
|
|
int16_t result = (first < second) ? 1 : 0;
|
|
D(3, "Comparing " << first << " + " << second << " = " << result);
|
|
*(int16_t *)(vd.data() + i) = result;
|
|
}
|
|
} else if (vtype_.vsew == 32) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
int32_t first = *(int32_t *)(vr1.data() + i);
|
|
int32_t second = *(int32_t *)(vr2.data() + i);
|
|
int32_t result = (first < second) ? 1 : 0;
|
|
D(3, "Comparing " << first << " + " << second << " = " << result);
|
|
*(int32_t *)(vd.data() + i) = result;
|
|
}
|
|
}
|
|
} break;
|
|
case 28: {
|
|
//vmsleu
|
|
auto &vr1 = vRegFile_[rsrc0];
|
|
auto &vr2 = vRegFile_[rsrc1];
|
|
auto &vd = vRegFile_[rdest];
|
|
if (vtype_.vsew == 8) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
uint8_t first = *(uint8_t *)(vr1.data() + i);
|
|
uint8_t second = *(uint8_t *)(vr2.data() + i);
|
|
uint8_t result = (first <= second) ? 1 : 0;
|
|
D(3, "Comparing " << first << " + " << second << " = " << result);
|
|
*(uint8_t *)(vd.data() + i) = result;
|
|
}
|
|
} else if (vtype_.vsew == 16) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
uint16_t first = *(uint16_t *)(vr1.data() + i);
|
|
uint16_t second = *(uint16_t *)(vr2.data() + i);
|
|
uint16_t result = (first <= second) ? 1 : 0;
|
|
D(3, "Comparing " << first << " + " << second << " = " << result);
|
|
*(uint16_t *)(vd.data() + i) = result;
|
|
}
|
|
} else if (vtype_.vsew == 32) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
uint32_t first = *(uint32_t *)(vr1.data() + i);
|
|
uint32_t second = *(uint32_t *)(vr2.data() + i);
|
|
uint32_t result = (first <= second) ? 1 : 0;
|
|
D(3, "Comparing " << first << " + " << second << " = " << result);
|
|
*(uint32_t *)(vd.data() + i) = result;
|
|
}
|
|
}
|
|
} break;
|
|
case 29: {
|
|
//vmsle
|
|
auto &vr1 = vRegFile_[rsrc0];
|
|
auto &vr2 = vRegFile_[rsrc1];
|
|
auto &vd = vRegFile_[rdest];
|
|
if (vtype_.vsew == 8) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
int8_t first = *(int8_t *)(vr1.data() + i);
|
|
int8_t second = *(int8_t *)(vr2.data() + i);
|
|
int8_t result = (first <= second) ? 1 : 0;
|
|
D(3, "Comparing " << first << " + " << second << " = " << result);
|
|
*(uint8_t *)(vd.data() + i) = result;
|
|
}
|
|
} else if (vtype_.vsew == 16) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
int16_t first = *(int16_t *)(vr1.data() + i);
|
|
int16_t second = *(int16_t *)(vr2.data() + i);
|
|
int16_t result = (first <= second) ? 1 : 0;
|
|
D(3, "Comparing " << first << " + " << second << " = " << result);
|
|
*(int16_t *)(vd.data() + i) = result;
|
|
}
|
|
} else if (vtype_.vsew == 32) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
int32_t first = *(int32_t *)(vr1.data() + i);
|
|
int32_t second = *(int32_t *)(vr2.data() + i);
|
|
int32_t result = (first <= second) ? 1 : 0;
|
|
D(3, "Comparing " << first << " + " << second << " = " << result);
|
|
*(int32_t *)(vd.data() + i) = result;
|
|
}
|
|
}
|
|
} break;
|
|
case 30: {
|
|
//vmsgtu
|
|
auto &vr1 = vRegFile_[rsrc0];
|
|
auto &vr2 = vRegFile_[rsrc1];
|
|
auto &vd = vRegFile_[rdest];
|
|
if (vtype_.vsew == 8) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
uint8_t first = *(uint8_t *)(vr1.data() + i);
|
|
uint8_t second = *(uint8_t *)(vr2.data() + i);
|
|
uint8_t result = (first > second) ? 1 : 0;
|
|
D(3, "Comparing " << first << " + " << second << " = " << result);
|
|
*(uint8_t *)(vd.data() + i) = result;
|
|
}
|
|
} else if (vtype_.vsew == 16) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
uint16_t first = *(uint16_t *)(vr1.data() + i);
|
|
uint16_t second = *(uint16_t *)(vr2.data() + i);
|
|
uint16_t result = (first > second) ? 1 : 0;
|
|
D(3, "Comparing " << first << " + " << second << " = " << result);
|
|
*(uint16_t *)(vd.data() + i) = result;
|
|
}
|
|
} else if (vtype_.vsew == 32) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
uint32_t first = *(uint32_t *)(vr1.data() + i);
|
|
uint32_t second = *(uint32_t *)(vr2.data() + i);
|
|
uint32_t result = (first > second) ? 1 : 0;
|
|
D(3, "Comparing " << first << " + " << second << " = " << result);
|
|
*(uint32_t *)(vd.data() + i) = result;
|
|
}
|
|
}
|
|
} break;
|
|
case 31: {
|
|
//vmsgt
|
|
auto &vr1 = vRegFile_[rsrc0];
|
|
auto &vr2 = vRegFile_[rsrc1];
|
|
auto &vd = vRegFile_[rdest];
|
|
if (vtype_.vsew == 8) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
int8_t first = *(int8_t *)(vr1.data() + i);
|
|
int8_t second = *(int8_t *)(vr2.data() + i);
|
|
int8_t result = (first > second) ? 1 : 0;
|
|
D(3, "Comparing " << first << " + " << second << " = " << result);
|
|
*(uint8_t *)(vd.data() + i) = result;
|
|
}
|
|
} else if (vtype_.vsew == 16) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
int16_t first = *(int16_t *)(vr1.data() + i);
|
|
int16_t second = *(int16_t *)(vr2.data() + i);
|
|
int16_t result = (first > second) ? 1 : 0;
|
|
D(3, "Comparing " << first << " + " << second << " = " << result);
|
|
*(int16_t *)(vd.data() + i) = result;
|
|
}
|
|
} else if (vtype_.vsew == 32) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
int32_t first = *(int32_t *)(vr1.data() + i);
|
|
int32_t second = *(int32_t *)(vr2.data() + i);
|
|
int32_t result = (first > second) ? 1 : 0;
|
|
D(3, "Comparing " << first << " + " << second << " = " << result);
|
|
*(int32_t *)(vd.data() + i) = result;
|
|
}
|
|
}
|
|
} break;
|
|
}
|
|
break;
|
|
case 2: {
|
|
switch (func6) {
|
|
case 24: {
|
|
// vmandnot
|
|
auto &vr1 = vRegFile_[rsrc0];
|
|
auto &vr2 = vRegFile_[rsrc1];
|
|
auto &vd = vRegFile_[rdest];
|
|
if (vtype_.vsew == 8) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
uint8_t first = *(uint8_t *)(vr1.data() + i);
|
|
uint8_t second = *(uint8_t *)(vr2.data() + i);
|
|
uint8_t first_value = (first & 0x1);
|
|
uint8_t second_value = (second & 0x1);
|
|
uint8_t result = (first_value & !second_value);
|
|
D(3, "Comparing " << first << " + " << second << " = " << result);
|
|
*(uint8_t *)(vd.data() + i) = result;
|
|
}
|
|
for (int i = vl_; i < VLMAX; i++) {
|
|
*(uint8_t *)(vd.data() + i) = 0;
|
|
}
|
|
} else if (vtype_.vsew == 16) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
uint16_t first = *(uint16_t *)(vr1.data() + i);
|
|
uint16_t second = *(uint16_t *)(vr2.data() + i);
|
|
uint16_t first_value = (first & 0x1);
|
|
uint16_t second_value = (second & 0x1);
|
|
uint16_t result = (first_value & !second_value);
|
|
D(3, "Comparing " << first << " + " << second << " = " << result);
|
|
*(uint16_t *)(vd.data() + i) = result;
|
|
}
|
|
for (int i = vl_; i < VLMAX; i++) {
|
|
*(uint16_t *)(vd.data() + i) = 0;
|
|
}
|
|
} else if (vtype_.vsew == 32) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
uint32_t first = *(uint32_t *)(vr1.data() + i);
|
|
uint32_t second = *(uint32_t *)(vr2.data() + i);
|
|
uint32_t first_value = (first & 0x1);
|
|
uint32_t second_value = (second & 0x1);
|
|
uint32_t result = (first_value & !second_value);
|
|
D(3, "Comparing " << first << " + " << second << " = " << result);
|
|
*(uint32_t *)(vd.data() + i) = result;
|
|
}
|
|
for (int i = vl_; i < VLMAX; i++) {
|
|
*(uint32_t *)(vd.data() + i) = 0;
|
|
}
|
|
}
|
|
} break;
|
|
case 25: {
|
|
// vmand
|
|
auto &vr1 = vRegFile_[rsrc0];
|
|
auto &vr2 = vRegFile_[rsrc1];
|
|
auto &vd = vRegFile_[rdest];
|
|
if (vtype_.vsew == 8) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
uint8_t first = *(uint8_t *)(vr1.data() + i);
|
|
uint8_t second = *(uint8_t *)(vr2.data() + i);
|
|
uint8_t first_value = (first & 0x1);
|
|
uint8_t second_value = (second & 0x1);
|
|
uint8_t result = (first_value & second_value);
|
|
D(3, "Comparing " << first << " + " << second << " = " << result);
|
|
*(uint8_t *)(vd.data() + i) = result;
|
|
}
|
|
for (int i = vl_; i < VLMAX; i++) {
|
|
*(uint8_t *)(vd.data() + i) = 0;
|
|
}
|
|
} else if (vtype_.vsew == 16) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
uint16_t first = *(uint16_t *)(vr1.data() + i);
|
|
uint16_t second = *(uint16_t *)(vr2.data() + i);
|
|
uint16_t first_value = (first & 0x1);
|
|
uint16_t second_value = (second & 0x1);
|
|
uint16_t result = (first_value & second_value);
|
|
D(3, "Comparing " << first << " + " << second << " = " << result);
|
|
*(uint16_t *)(vd.data() + i) = result;
|
|
}
|
|
for (int i = vl_; i < VLMAX; i++) {
|
|
*(uint16_t *)(vd.data() + i) = 0;
|
|
}
|
|
} else if (vtype_.vsew == 32) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
uint32_t first = *(uint32_t *)(vr1.data() + i);
|
|
uint32_t second = *(uint32_t *)(vr2.data() + i);
|
|
uint32_t first_value = (first & 0x1);
|
|
uint32_t second_value = (second & 0x1);
|
|
uint32_t result = (first_value & second_value);
|
|
D(3, "Comparing " << first << " + " << second << " = " << result);
|
|
*(uint32_t *)(vd.data() + i) = result;
|
|
}
|
|
for (int i = vl_; i < VLMAX; i++) {
|
|
*(uint32_t *)(vd.data() + i) = 0;
|
|
}
|
|
}
|
|
} break;
|
|
case 26: {
|
|
// vmor
|
|
auto &vr1 = vRegFile_[rsrc0];
|
|
auto &vr2 = vRegFile_[rsrc1];
|
|
auto &vd = vRegFile_[rdest];
|
|
if (vtype_.vsew == 8) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
uint8_t first = *(uint8_t *)(vr1.data() + i);
|
|
uint8_t second = *(uint8_t *)(vr2.data() + i);
|
|
uint8_t first_value = (first & 0x1);
|
|
uint8_t second_value = (second & 0x1);
|
|
uint8_t result = (first_value | second_value);
|
|
D(3, "Comparing " << first << " + " << second << " = " << result);
|
|
*(uint8_t *)(vd.data() + i) = result;
|
|
}
|
|
for (int i = vl_; i < VLMAX; i++) {
|
|
*(uint8_t *)(vd.data() + i) = 0;
|
|
}
|
|
} else if (vtype_.vsew == 16) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
uint16_t first = *(uint16_t *)(vr1.data() + i);
|
|
uint16_t second = *(uint16_t *)(vr2.data() + i);
|
|
uint16_t first_value = (first & 0x1);
|
|
uint16_t second_value = (second & 0x1);
|
|
uint16_t result = (first_value | second_value);
|
|
D(3, "Comparing " << first << " + " << second << " = " << result);
|
|
*(uint16_t *)(vd.data() + i) = result;
|
|
}
|
|
for (int i = vl_; i < VLMAX; i++) {
|
|
*(uint16_t *)(vd.data() + i) = 0;
|
|
}
|
|
} else if (vtype_.vsew == 32) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
uint32_t first = *(uint32_t *)(vr1.data() + i);
|
|
uint32_t second = *(uint32_t *)(vr2.data() + i);
|
|
uint32_t first_value = (first & 0x1);
|
|
uint32_t second_value = (second & 0x1);
|
|
uint32_t result = (first_value | second_value);
|
|
D(3, "Comparing " << first << " + " << second << " = " << result);
|
|
*(uint32_t *)(vd.data() + i) = result;
|
|
}
|
|
for (int i = vl_; i < VLMAX; i++) {
|
|
*(uint32_t *)(vd.data() + i) = 0;
|
|
}
|
|
}
|
|
} break;
|
|
case 27: {
|
|
//vmxor
|
|
auto &vr1 = vRegFile_[rsrc0];
|
|
auto &vr2 = vRegFile_[rsrc1];
|
|
auto &vd = vRegFile_[rdest];
|
|
if (vtype_.vsew == 8) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
uint8_t first = *(uint8_t *)(vr1.data() + i);
|
|
uint8_t second = *(uint8_t *)(vr2.data() + i);
|
|
uint8_t first_value = (first & 0x1);
|
|
uint8_t second_value = (second & 0x1);
|
|
uint8_t result = (first_value ^ second_value);
|
|
D(3, "Comparing " << first << " + " << second << " = " << result);
|
|
*(uint8_t *)(vd.data() + i) = result;
|
|
}
|
|
for (int i = vl_; i < VLMAX; i++) {
|
|
*(uint8_t *)(vd.data() + i) = 0;
|
|
}
|
|
} else if (vtype_.vsew == 16) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
uint16_t first = *(uint16_t *)(vr1.data() + i);
|
|
uint16_t second = *(uint16_t *)(vr2.data() + i);
|
|
uint16_t first_value = (first & 0x1);
|
|
uint16_t second_value = (second & 0x1);
|
|
uint16_t result = (first_value ^ second_value);
|
|
D(3, "Comparing " << first << " + " << second << " = " << result);
|
|
*(uint16_t *)(vd.data() + i) = result;
|
|
}
|
|
for (int i = vl_; i < VLMAX; i++) {
|
|
*(uint16_t *)(vd.data() + i) = 0;
|
|
}
|
|
} else if (vtype_.vsew == 32) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
uint32_t first = *(uint32_t *)(vr1.data() + i);
|
|
uint32_t second = *(uint32_t *)(vr2.data() + i);
|
|
uint32_t first_value = (first & 0x1);
|
|
uint32_t second_value = (second & 0x1);
|
|
uint32_t result = (first_value ^ second_value);
|
|
D(3, "Comparing " << first << " + " << second << " = " << result);
|
|
*(uint32_t *)(vd.data() + i) = result;
|
|
}
|
|
for (int i = vl_; i < VLMAX; i++) {
|
|
*(uint32_t *)(vd.data() + i) = 0;
|
|
}
|
|
}
|
|
} break;
|
|
case 28: {
|
|
//vmornot
|
|
auto &vr1 = vRegFile_[rsrc0];
|
|
auto &vr2 = vRegFile_[rsrc1];
|
|
auto &vd = vRegFile_[rdest];
|
|
if (vtype_.vsew == 8) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
uint8_t first = *(uint8_t *)(vr1.data() + i);
|
|
uint8_t second = *(uint8_t *)(vr2.data() + i);
|
|
uint8_t first_value = (first & 0x1);
|
|
uint8_t second_value = (second & 0x1);
|
|
uint8_t result = (first_value | !second_value);
|
|
D(3, "Comparing " << first << " + " << second << " = " << result);
|
|
*(uint8_t *)(vd.data() + i) = result;
|
|
}
|
|
for (int i = vl_; i < VLMAX; i++) {
|
|
*(uint8_t *)(vd.data() + i) = 0;
|
|
}
|
|
} else if (vtype_.vsew == 16) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
uint16_t first = *(uint16_t *)(vr1.data() + i);
|
|
uint16_t second = *(uint16_t *)(vr2.data() + i);
|
|
uint16_t first_value = (first & 0x1);
|
|
uint16_t second_value = (second & 0x1);
|
|
uint16_t result = (first_value | !second_value);
|
|
D(3, "Comparing " << first << " + " << second << " = " << result);
|
|
*(uint16_t *)(vd.data() + i) = result;
|
|
}
|
|
for (int i = vl_; i < VLMAX; i++) {
|
|
*(uint16_t *)(vd.data() + i) = 0;
|
|
}
|
|
} else if (vtype_.vsew == 32) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
uint32_t first = *(uint32_t *)(vr1.data() + i);
|
|
uint32_t second = *(uint32_t *)(vr2.data() + i);
|
|
uint32_t first_value = (first & 0x1);
|
|
uint32_t second_value = (second & 0x1);
|
|
uint32_t result = (first_value | !second_value);
|
|
D(3, "Comparing " << first << " + " << second << " = " << result);
|
|
*(uint32_t *)(vd.data() + i) = result;
|
|
}
|
|
for (int i = vl_; i < VLMAX; i++) {
|
|
*(uint32_t *)(vd.data() + i) = 0;
|
|
}
|
|
}
|
|
} break;
|
|
case 29: {
|
|
//vmnand
|
|
auto &vr1 = vRegFile_[rsrc0];
|
|
auto &vr2 = vRegFile_[rsrc1];
|
|
auto &vd = vRegFile_[rdest];
|
|
if (vtype_.vsew == 8) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
uint8_t first = *(uint8_t *)(vr1.data() + i);
|
|
uint8_t second = *(uint8_t *)(vr2.data() + i);
|
|
uint8_t first_value = (first & 0x1);
|
|
uint8_t second_value = (second & 0x1);
|
|
uint8_t result = !(first_value & second_value);
|
|
D(3, "Comparing " << first << " + " << second << " = " << result);
|
|
*(uint8_t *)(vd.data() + i) = result;
|
|
}
|
|
for (int i = vl_; i < VLMAX; i++) {
|
|
*(uint8_t *)(vd.data() + i) = 0;
|
|
}
|
|
} else if (vtype_.vsew == 16) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
uint16_t first = *(uint16_t *)(vr1.data() + i);
|
|
uint16_t second = *(uint16_t *)(vr2.data() + i);
|
|
uint16_t first_value = (first & 0x1);
|
|
uint16_t second_value = (second & 0x1);
|
|
uint16_t result = !(first_value & second_value);
|
|
D(3, "Comparing " << first << " + " << second << " = " << result);
|
|
*(uint16_t *)(vd.data() + i) = result;
|
|
}
|
|
for (int i = vl_; i < VLMAX; i++) {
|
|
*(uint16_t *)(vd.data() + i) = 0;
|
|
}
|
|
} else if (vtype_.vsew == 32) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
uint32_t first = *(uint32_t *)(vr1.data() + i);
|
|
uint32_t second = *(uint32_t *)(vr2.data() + i);
|
|
uint32_t first_value = (first & 0x1);
|
|
uint32_t second_value = (second & 0x1);
|
|
uint32_t result = !(first_value & second_value);
|
|
D(3, "Comparing " << first << " + " << second << " = " << result);
|
|
*(uint32_t *)(vd.data() + i) = result;
|
|
}
|
|
for (int i = vl_; i < VLMAX; i++) {
|
|
*(uint32_t *)(vd.data() + i) = 0;
|
|
}
|
|
}
|
|
} break;
|
|
case 30: {
|
|
//vmnor
|
|
auto &vr1 = vRegFile_[rsrc0];
|
|
auto &vr2 = vRegFile_[rsrc1];
|
|
auto &vd = vRegFile_[rdest];
|
|
if (vtype_.vsew == 8) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
uint8_t first = *(uint8_t *)(vr1.data() + i);
|
|
uint8_t second = *(uint8_t *)(vr2.data() + i);
|
|
uint8_t first_value = (first & 0x1);
|
|
uint8_t second_value = (second & 0x1);
|
|
uint8_t result = !(first_value | second_value);
|
|
D(3, "Comparing " << first << " + " << second << " = " << result);
|
|
*(uint8_t *)(vd.data() + i) = result;
|
|
}
|
|
for (int i = vl_; i < VLMAX; i++) {
|
|
*(uint8_t *)(vd.data() + i) = 0;
|
|
}
|
|
} else if (vtype_.vsew == 16) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
uint16_t first = *(uint16_t *)(vr1.data() + i);
|
|
uint16_t second = *(uint16_t *)(vr2.data() + i);
|
|
uint16_t first_value = (first & 0x1);
|
|
uint16_t second_value = (second & 0x1);
|
|
uint16_t result = !(first_value | second_value);
|
|
D(3, "Comparing " << first << " + " << second << " = " << result);
|
|
*(uint16_t *)(vd.data() + i) = result;
|
|
}
|
|
for (int i = vl_; i < VLMAX; i++) {
|
|
*(uint16_t *)(vd.data() + i) = 0;
|
|
}
|
|
} else if (vtype_.vsew == 32) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
uint32_t first = *(uint32_t *)(vr1.data() + i);
|
|
uint32_t second = *(uint32_t *)(vr2.data() + i);
|
|
uint32_t first_value = (first & 0x1);
|
|
uint32_t second_value = (second & 0x1);
|
|
uint32_t result = !(first_value | second_value);
|
|
D(3, "Comparing " << first << " + " << second << " = " << result);
|
|
*(uint32_t *)(vd.data() + i) = result;
|
|
}
|
|
for (int i = vl_; i < VLMAX; i++) {
|
|
*(uint32_t *)(vd.data() + i) = 0;
|
|
}
|
|
}
|
|
} break;
|
|
case 31: {
|
|
//vmxnor
|
|
auto &vr1 = vRegFile_[rsrc0];
|
|
auto &vr2 = vRegFile_[rsrc1];
|
|
auto &vd = vRegFile_[rdest];
|
|
if (vtype_.vsew == 8) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
uint8_t first = *(uint8_t *)(vr1.data() + i);
|
|
uint8_t second = *(uint8_t *)(vr2.data() + i);
|
|
uint8_t first_value = (first & 0x1);
|
|
uint8_t second_value = (second & 0x1);
|
|
uint8_t result = !(first_value ^ second_value);
|
|
D(3, "Comparing " << first << " + " << second << " = " << result);
|
|
*(uint8_t *)(vd.data() + i) = result;
|
|
}
|
|
for (int i = vl_; i < VLMAX; i++) {
|
|
*(uint8_t *)(vd.data() + i) = 0;
|
|
}
|
|
} else if (vtype_.vsew == 16) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
uint16_t first = *(uint16_t *)(vr1.data() + i);
|
|
uint16_t second = *(uint16_t *)(vr2.data() + i);
|
|
uint16_t first_value = (first & 0x1);
|
|
uint16_t second_value = (second & 0x1);
|
|
uint16_t result = !(first_value ^ second_value);
|
|
D(3, "Comparing " << first << " + " << second << " = " << result);
|
|
*(uint16_t *)(vd.data() + i) = result;
|
|
}
|
|
for (int i = vl_; i < VLMAX; i++) {
|
|
*(uint16_t *)(vd.data() + i) = 0;
|
|
}
|
|
} else if (vtype_.vsew == 32) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
uint32_t first = *(uint32_t *)(vr1.data() + i);
|
|
uint32_t second = *(uint32_t *)(vr2.data() + i);
|
|
uint32_t first_value = (first & 0x1);
|
|
uint32_t second_value = (second & 0x1);
|
|
uint32_t result = !(first_value ^ second_value);
|
|
D(3, "Comparing " << first << " + " << second << " = " << result);
|
|
*(uint32_t *)(vd.data() + i) = result;
|
|
}
|
|
for (int i = vl_; i < VLMAX; i++) {
|
|
*(uint32_t *)(vd.data() + i) = 0;
|
|
}
|
|
}
|
|
} break;
|
|
case 37: {
|
|
//vmul
|
|
auto &vr1 = vRegFile_[rsrc0];
|
|
auto &vr2 = vRegFile_[rsrc1];
|
|
auto &vd = vRegFile_[rdest];
|
|
if (vtype_.vsew == 8) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
uint8_t first = *(uint8_t *)(vr1.data() + i);
|
|
uint8_t second = *(uint8_t *)(vr2.data() + i);
|
|
uint8_t result = (first * second);
|
|
D(3, "Comparing " << first << " + " << second << " = " << result);
|
|
*(uint8_t *)(vd.data() + i) = result;
|
|
}
|
|
for (int i = vl_; i < VLMAX; i++) {
|
|
*(uint8_t *)(vd.data() + i) = 0;
|
|
}
|
|
} else if (vtype_.vsew == 16) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
uint16_t first = *(uint16_t *)(vr1.data() + i);
|
|
uint16_t second = *(uint16_t *)(vr2.data() + i);
|
|
uint16_t result = (first * second);
|
|
D(3, "Comparing " << first << " + " << second << " = " << result);
|
|
*(uint16_t *)(vd.data() + i) = result;
|
|
}
|
|
for (int i = vl_; i < VLMAX; i++) {
|
|
*(uint16_t *)(vd.data() + i) = 0;
|
|
}
|
|
} else if (vtype_.vsew == 32) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
uint32_t first = *(uint32_t *)(vr1.data() + i);
|
|
uint32_t second = *(uint32_t *)(vr2.data() + i);
|
|
uint32_t result = (first * second);
|
|
D(3, "Comparing " << first << " + " << second << " = " << result);
|
|
*(uint32_t *)(vd.data() + i) = result;
|
|
}
|
|
for (int i = vl_; i < VLMAX; i++) {
|
|
*(uint32_t *)(vd.data() + i) = 0;
|
|
}
|
|
}
|
|
} break;
|
|
case 45: {
|
|
// vmacc
|
|
auto &vr1 = vRegFile_[rsrc0];
|
|
auto &vr2 = vRegFile_[rsrc1];
|
|
auto &vd = vRegFile_[rdest];
|
|
if (vtype_.vsew == 8) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
uint8_t first = *(uint8_t *)(vr1.data() + i);
|
|
uint8_t second = *(uint8_t *)(vr2.data() + i);
|
|
uint8_t result = (first * second);
|
|
D(3, "Comparing " << first << " + " << second << " = " << result);
|
|
*(uint8_t *)(vd.data() + i) += result;
|
|
}
|
|
for (int i = vl_; i < VLMAX; i++) {
|
|
*(uint8_t *)(vd.data() + i) = 0;
|
|
}
|
|
} else if (vtype_.vsew == 16) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
uint16_t first = *(uint16_t *)(vr1.data() + i);
|
|
uint16_t second = *(uint16_t *)(vr2.data() + i);
|
|
uint16_t result = (first * second);
|
|
D(3, "Comparing " << first << " + " << second << " = " << result);
|
|
*(uint16_t *)(vd.data() + i) += result;
|
|
}
|
|
for (int i = vl_; i < VLMAX; i++) {
|
|
*(uint16_t *)(vd.data() + i) = 0;
|
|
}
|
|
} else if (vtype_.vsew == 32) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
uint32_t first = *(uint32_t *)(vr1.data() + i);
|
|
uint32_t second = *(uint32_t *)(vr2.data() + i);
|
|
uint32_t result = (first * second);
|
|
D(3, "Comparing " << first << " + " << second << " = " << result);
|
|
*(uint32_t *)(vd.data() + i) += result;
|
|
}
|
|
for (int i = vl_; i < VLMAX; i++) {
|
|
*(uint32_t *)(vd.data() + i) = 0;
|
|
}
|
|
}
|
|
} break;
|
|
}
|
|
} break;
|
|
case 6: {
|
|
switch (func6) {
|
|
case 0: {
|
|
auto &vr2 = vRegFile_[rsrc1];
|
|
auto &vd = vRegFile_[rdest];
|
|
if (vtype_.vsew == 8) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
uint8_t second = *(uint8_t *)(vr2.data() + i);
|
|
uint8_t result = (rsdata[0] + second);
|
|
D(3, "Comparing " << rsdata[0] << " + " << second << " = " << result);
|
|
*(uint8_t *)(vd.data() + i) = result;
|
|
}
|
|
for (int i = vl_; i < VLMAX; i++) {
|
|
*(uint8_t *)(vd.data() + i) = 0;
|
|
}
|
|
} else if (vtype_.vsew == 16) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
uint16_t second = *(uint16_t *)(vr2.data() + i);
|
|
uint16_t result = (rsdata[0] + second);
|
|
D(3, "Comparing " << rsdata[0] << " + " << second << " = " << result);
|
|
*(uint16_t *)(vd.data() + i) = result;
|
|
}
|
|
for (int i = vl_; i < VLMAX; i++) {
|
|
*(uint16_t *)(vd.data() + i) = 0;
|
|
}
|
|
} else if (vtype_.vsew == 32) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
uint32_t second = *(uint32_t *)(vr2.data() + i);
|
|
uint32_t result = (rsdata[0] + second);
|
|
D(3, "Comparing " << rsdata[0] << " + " << second << " = " << result);
|
|
*(uint32_t *)(vd.data() + i) = result;
|
|
}
|
|
for (int i = vl_; i < VLMAX; i++) {
|
|
*(uint32_t *)(vd.data() + i) = 0;
|
|
}
|
|
}
|
|
} break;
|
|
case 37: {
|
|
// vmul.vx
|
|
auto &vr2 = vRegFile_[rsrc1];
|
|
auto &vd = vRegFile_[rdest];
|
|
if (vtype_.vsew == 8) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
uint8_t second = *(uint8_t *)(vr2.data() + i);
|
|
uint8_t result = (rsdata[0] * second);
|
|
D(3, "Comparing " << rsdata[0] << " + " << second << " = " << result);
|
|
*(uint8_t *)(vd.data() + i) = result;
|
|
}
|
|
for (int i = vl_; i < VLMAX; i++) {
|
|
*(uint8_t *)(vd.data() + i) = 0;
|
|
}
|
|
} else if (vtype_.vsew == 16) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
uint16_t second = *(uint16_t *)(vr2.data() + i);
|
|
uint16_t result = (rsdata[0] * second);
|
|
D(3, "Comparing " << rsdata[0] << " + " << second << " = " << result);
|
|
*(uint16_t *)(vd.data() + i) = result;
|
|
}
|
|
for (int i = vl_; i < VLMAX; i++) {
|
|
*(uint16_t *)(vd.data() + i) = 0;
|
|
}
|
|
} else if (vtype_.vsew == 32) {
|
|
for (int i = 0; i < vl_; i++) {
|
|
uint32_t second = *(uint32_t *)(vr2.data() + i);
|
|
uint32_t result = (rsdata[0] * second);
|
|
D(3, "Comparing " << rsdata[0] << " + " << second << " = " << result);
|
|
*(uint32_t *)(vd.data() + i) = result;
|
|
}
|
|
for (int i = vl_; i < VLMAX; i++) {
|
|
*(uint32_t *)(vd.data() + i) = 0;
|
|
}
|
|
}
|
|
} break;
|
|
}
|
|
} break;
|
|
case 7: {
|
|
vtype_.vill = 0;
|
|
vtype_.vediv = instr.getVediv();
|
|
vtype_.vsew = instr.getVsew();
|
|
vtype_.vlmul = instr.getVlmul();
|
|
|
|
D(3, "lmul:" << vtype_.vlmul << " sew:" << vtype_.vsew << " ediv: " << vtype_.vediv << "rsrc_" << rsdata[0] << "VLMAX" << VLMAX);
|
|
|
|
int s0 = rsdata[0];
|
|
if (s0 <= VLMAX) {
|
|
vl_ = s0;
|
|
} else if (s0 < (2 * VLMAX)) {
|
|
vl_ = (int)ceil((s0 * 1.0) / 2.0);
|
|
} else if (s0 >= (2 * VLMAX)) {
|
|
vl_ = VLMAX;
|
|
}
|
|
rddata = vl_;
|
|
} break;
|
|
default:
|
|
std::abort();
|
|
}
|
|
} break;
|
|
default:
|
|
std::abort();
|
|
}
|
|
|
|
if (rd_write) {
|
|
int rdt = instr.getRDType();
|
|
switch (rdt) {
|
|
case 1:
|
|
if (rdest) {
|
|
D(2, "[" << std::dec << t << "] Dest Regs: r" << rdest << "=0x" << std::hex << std::hex << rddata);
|
|
iregs[rdest] = rddata;
|
|
}
|
|
break;
|
|
case 2:
|
|
D(2, "[" << std::dec << t << "] Dest Regs: fr" << rdest << "=0x" << std::hex << std::hex << rddata);
|
|
fregs[rdest] = rddata;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
// simx64
|
|
PC_ += 4;
|
|
if (PC_ != nextPC) {
|
|
D(3, "*** Next PC: " << std::hex << nextPC << std::dec);
|
|
PC_ = nextPC;
|
|
}
|
|
}
|