17 lines
368 B
Verilog
17 lines
368 B
Verilog
`ifndef VX_WB_IF
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`define VX_WB_IF
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`include "VX_define.vh"
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interface VX_wb_if ();
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wire [`NUM_THREADS-1:0] valid;
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wire [`NUM_THREADS-1:0][31:0] data;
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wire [`NW_BITS-1:0] warp_num;
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wire [4:0] rd;
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wire [1:0] wb;
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wire [31:0] curr_PC;
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endinterface
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`endif |