59 lines
1.4 KiB
Verilog
59 lines
1.4 KiB
Verilog
`include "VX_platform.vh"
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module VX_elastic_buffer #(
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parameter DATAW = 1,
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parameter SIZE = 2,
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parameter BUFFERED = 0,
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parameter FASTRAM = 0,
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parameter PASSTHRU = 0
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) (
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input wire clk,
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input wire reset,
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input wire valid_in,
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output wire ready_in,
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input wire [DATAW-1:0] data_in,
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output wire [DATAW-1:0] data_out,
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input wire ready_out,
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output wire valid_out
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);
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if (PASSTHRU) begin
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`UNUSED_VAR (clk)
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`UNUSED_VAR (reset)
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assign valid_out = valid_in;
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assign data_out = data_in;
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assign ready_in = ready_out;
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end else begin
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wire empty, full;
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wire push = valid_in && ready_in;
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wire pop = valid_out && ready_out;
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VX_fifo_queue #(
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.DATAW (DATAW),
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.SIZE (SIZE),
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.BUFFERED (BUFFERED),
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.FASTRAM (FASTRAM)
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) queue (
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.clk (clk),
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.reset (reset),
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.push (push),
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.pop (pop),
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.data_in(data_in),
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.data_out(data_out),
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.empty (empty),
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.full (full),
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`UNUSED_PIN (size)
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);
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assign ready_in = ~full;
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assign valid_out = ~empty;
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end
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endmodule |