wu-arch/vortex
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
cb0459a960eb75b9825db602f2ecfe3eef0fffc7
vortex/hw/rtl/libs
History
Blaise Tine 47c3234659 minor update
2021-06-13 10:58:48 -07:00
..
VX_bypass_buffer.v
reset networks optimization
2020-11-16 01:12:02 -08:00
VX_divider.v
multiplier unit optimization - using fifo for metadata, shift register optimization
2020-12-26 11:23:21 -08:00
VX_dp_ram.v
Merge branch 'master' of https://github.gatech.edu/casl/Vortex
2021-03-04 20:51:03 -08:00
VX_elastic_buffer.v
minor updates
2021-01-17 13:58:43 -08:00
VX_fair_arbiter.v
adding input buffering to bus arbiters to reduce backpressure delay propagation
2020-12-05 17:31:29 -08:00
VX_fifo_queue.v
minor update
2021-02-27 02:31:05 -08:00
VX_fixed_arbiter.v
Merge branch 'master' of https://github.gatech.edu/casl/Vortex
2021-03-04 20:51:03 -08:00
VX_index_buffer.v
adding empty to index_buffer
2021-03-30 10:15:42 -07:00
VX_index_queue.v
reset networks optimization
2020-11-16 01:12:02 -08:00
VX_lzc.v
minor update
2021-01-10 22:03:23 -08:00
VX_matrix_arbiter.v
lkg build rollout with 16cores optimization on arria10
2021-01-24 16:49:22 -08:00
VX_multiplier.v
RAM blocks inference fixes
2020-11-30 14:02:47 -08:00
VX_onehot_encoder.v
lkg build rollout with 16cores optimization on arria10
2021-01-24 16:49:22 -08:00
VX_pending_size.v
minor updates
2021-01-12 11:24:36 -08:00
VX_pipe_register.v
fixed pipe register reset issue in synthesis
2021-01-01 14:54:18 -08:00
VX_priority_encoder.v
non-cacheable memory address critical paths optimizations
2021-06-10 12:47:18 -07:00
VX_reset_relay.v
updating fdiv/fsqrt bram hex files, reset_delay updaet
2021-02-04 09:02:18 -08:00
VX_rr_arbiter.v
lkg build rollout with 16cores optimization on arria10
2021-01-24 16:49:22 -08:00
VX_scan.v
lkg build rollout with 16cores optimization on arria10
2021-01-24 16:49:22 -08:00
VX_scope.v
minor ibuffer critical path optimization.
2021-04-19 20:53:13 -07:00
VX_serial_div.v
reset networks optimization
2020-11-16 01:12:02 -08:00
VX_shift_register.v
lkg build rollout with 16cores optimization on arria10
2021-01-24 16:49:22 -08:00
VX_skid_buffer.v
minor update
2021-06-13 10:58:48 -07:00
VX_sp_ram.v
Merge branch 'master' of https://github.gatech.edu/casl/Vortex
2021-03-04 20:51:03 -08:00
VX_stream_arbiter.v
non-cacheable memory address critical paths optimizations
2021-06-10 12:47:18 -07:00
VX_stream_demux.v
using shiftreg-based skid buffers
2021-02-28 02:20:09 -08:00