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c3c9a4b5d831b0c05ab66142c3ebdada3dd0462d
vortex/hw/rtl/cache
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Hansung Kim c3c9a4b5d8 [BUGFIX] Fix wrong bitwidth of way_idx when NUM_WAYS=1 
When NUM_WAYS=1, CLOG2(NUM_WAYS)-1 becomes -1, setting the MSB of
way_idx to a wrong value.
2023-11-28 16:05:41 -08:00
..
VX_cache_bank.sv
Vortex 2.0 changes:
2023-10-19 20:51:22 -07:00
VX_cache_bypass.sv
Vortex 2.0 changes:
2023-10-19 20:51:22 -07:00
VX_cache_cluster_top.sv
hw unit tests fixes
2023-11-05 18:51:31 -08:00
VX_cache_cluster.sv
Move force-include of gpu_pkg to non-cache modules
2023-11-15 22:02:44 -08:00
VX_cache_data.sv
[BUGFIX] Fix wrong bitwidth of way_idx when NUM_WAYS=1
2023-11-28 16:05:41 -08:00
VX_cache_define.vh
Force-include gpu_pkg in VX_cache_define.vh
2023-11-28 13:55:11 -08:00
VX_cache_init.sv
Vortex 2.0 changes:
2023-10-19 20:51:22 -07:00
VX_cache_mshr.sv
Vortex 2.0 changes:
2023-10-19 20:51:22 -07:00
VX_cache_tags.sv
Vortex 2.0 changes:
2023-10-19 20:51:22 -07:00
VX_cache_top.sv
hw unit tests fixes
2023-11-05 18:51:31 -08:00
VX_cache_wrap.sv
cache bindings and memory perf refactory
2023-11-03 08:18:18 -04:00
VX_cache.sv
cache bindings and memory perf refactory
2023-11-03 08:18:18 -04:00